NoC design with DFG model for DSPS
2010 (English)In: Proceedings - International Conference on Electrical and Control Engineering, ICECE 2010, 2010, 3917-3920 p.Conference paper (Refereed)
The mapping design of network on chip (NoC) is one of the cores of SoC design for digital signal process system (DSPS). A NoC mapping method based on data flow graph (DFG) is addressed in this paper. For modules of heterogeneous processors, central memory, and IPs (intellectual properties), DFG model analysis shows that DFG model provides important data transmission properties included the direction and contents of data transmitting, requirements of synchronization and speed of data transmission. The DFG model, therefore, can be the base of route mapping design for the NoC. In addition, node architecture of simple router used in generic regulable NoC (GRNoC) is also proposed in this paper. The simple router can increases the properties of data transmission in NoC and is more suitable for mapping design with DFG model.
Place, publisher, year, edition, pages
2010. 3917-3920 p.
DFG, DSPS, NoC, SoC
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-150022DOI: 10.1109/iCECE.2010.954ScopusID: 2-s2.0-79952212739ISBN: 978-076954031-3OAI: oai:DiVA.org:kth-150022DiVA: diva2:743622
International Conference on Electrical and Control Engineering, ICECE 2010, 26 June 2010 through 28 June 2010, Wuhan, China
QC 201409042014-09-042014-08-292014-09-04Bibliographically approved