Area-efficient high-coverage LBIST
2014 (English)In: Microprocessors and microsystems, ISSN 0141-9331, E-ISSN 1872-9436, Vol. 38, no 5, 368-374 p.Article in journal (Refereed) Published
Logic Built-In Self Test (LBIST) is a popular technique for applications requiring in-field testing of digital circuits. LBIST incorporates test generation and response-capture on-chip. It requires no interaction with a large, expensive tester. LBIST offers test time reduction due to at-speed test pattern application, makes possible test data re-usability at many levels, and enables test-ready IP. However, the traditional pseudo-random pattern-based LBIST often has a low test coverage. This paper presents a new method for on-chip generation of deterministic test patterns based on registers with non-linear update. Our experimental results on 7 real designs show that the presented approach can achieve a higher stuck-at coverage than the test point insertion with less area overhead. We also show that registers with non-linear update are asymptotically smaller than memories required to store the same test patterns in a compressed form.
Place, publisher, year, edition, pages
2014. Vol. 38, no 5, 368-374 p.
LBIST, LFSR, Top-off test patterns, In-field testing, Test compression
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-150537DOI: 10.1016/j.micpro.2014.05.002ISI: 000340300900002ScopusID: 2-s2.0-84901824272OAI: oai:DiVA.org:kth-150537DiVA: diva2:744382
QC 201409082014-09-082014-09-052015-05-08Bibliographically approved