Low-latency and low-overhead mesochronous and plesiochronous synchronizers
2011 (English)Conference paper (Refereed)
In this paper we present efficient Mesochronous and Plesiochronous interfaces targeting low-latency and low-overhead links. Our source-synchronous scheme can easily be integrated in traditional design flows, supports maximal throughput, has low latency and has an overhead of only three flipflops per data line. With one additional flipflop per data line, the Plesiochronous interface allows the synchronizer to cope with clock drifts. The simple synchronization scheme is validated through formal analysis and simulation.
Place, publisher, year, edition, pages
2011. 157-164 p.
, Proceedings - 2011 14th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2011
Latency, Mesochronous, Ple-siochronous, Synchronizers, Clock drift, Data line, Design flows, Formal analysis, Low-latency, Maximal throughput, Synchronization scheme, Design, Systems analysis, Wireless sensor networks, Synchronization
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-150690DOI: 10.1109/DSD.2011.24ScopusID: 2-s2.0-80054979546ISBN: 9780769544946OAI: oai:DiVA.org:kth-150690DiVA: diva2:744387
2011 14th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2011, 31 August 2011 through 2 September 2011, Oulu
QC 201409082014-09-082014-09-082014-09-08Bibliographically approved