A survey of memory architecture for 3D chip multi-processors
2014 (English)In: Microprocessors and microsystems, ISSN 0141-9331, E-ISSN 1872-9436, Vol. 38, no 5, 415-430 p.Article in journal (Refereed) Published
3D chip multi-processors (3D CMPs) combine the advantages of 3D integration and the parallelism of CMPs, which are emerging as active research topics in VLSI and multi-core computer architecture communities. One significant potentiality of 3D CMPs is to exploit the diversity of integration processes and high volume of vertical TSV bandwidth to mitigate the well-known "Memory Wall" problem. Meanwhile, the 3D integration techniques are under the severe thermal, manufacture yield and cost constraints. Research on 3D stacking memory hierarchy explores the high performance and power/thermal efficient memory architectures for 3D CMPs. The micro-architectures of memories can be designed in the 3D integrated circuit context and integrated into 3D CMPs. This paper surveys the design of memory architectures for 3D CMPs. We summarize current research into two categories: stacking cache-only architectures and stacking main memory architectures for 3D CMPs. The representative works are reviewed and the remaining opportunities and challenges are discussed to guide the future research in this emerging area.
Place, publisher, year, edition, pages
2014. Vol. 38, no 5, 415-430 p.
3D integrated circuit, Chip multi-processor, Memory architecture, Non-uniform cache architecture
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-150538DOI: 10.1016/j.micpro.2014.03.007ISI: 000340300900005ScopusID: 2-s2.0-84903304051OAI: oai:DiVA.org:kth-150538DiVA: diva2:744589
QC 201409082014-09-082014-09-052014-09-08Bibliographically approved