A high-ELD tolerant continuous-time sigma-delta modulator for bluetooth with DWA calibration
2011 (English)In: Eur. Conf. Circuit Theory Des., ECCTD, 2011, 270-273 p.Conference paper (Refereed)
A Continuous-Time Sigma-Delta (ΣΔ) Modulator for Bluetooth with 52MHz sampling frequency in a 1.2V 65nm CMOS process is presented. The modulator has a proposed single-stage 3 rd-order 4-bit architecture, which employs a dual-loop feedback method to compensate the loop delay up to one clock period. A 4-bit flash ADC and a 4-bit current-steering DAC are used to improve the resolution and stability. Non-Return-Zero (NRZ) pulse shape of feedback-DAC is adopted to alleviate jitter sensitivity. Feedforward gains of the loop filter are realized by capacitors ratios. This approach can reduce the power consumption and provide better linearity. The basic data-weighted- averaging (DWA) digital linearization circuit is used to compensate the DAC mismatch errors efficiently. The co-simulation result at circuit level can achieve 80dB DR within 1MHz signal bandwidth without clock jitter or device noise.
Place, publisher, year, edition, pages
2011. 270-273 p.
, 2011 20th European Conference on Circuit Theory and Design, ECCTD 2011
Analog-to-Digital convector, capacitor ratio feedforward, continuous-time, delta-sigma, DWA, ELD, Analog-to-digital, Capacitor ratio, Continuous time, Bluetooth, Capacitors, Circuit theory, CMOS integrated circuits, Continuous time systems, Jitter, Modulators
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-150684DOI: 10.1109/ECCTD.2011.6043334ScopusID: 2-s2.0-80155138058ISBN: 9781457706189OAI: oai:DiVA.org:kth-150684DiVA: diva2:744886
2011 20th European Conference on Circuit Theory and Design, ECCTD 2011, 29 August 2011 through 31 August 2011, Linkoping, Sweden
QC 201409092014-09-092014-09-082014-09-09Bibliographically approved