A deadlock-free fault-tolerant routing algorithm based on pseudo-receiving mechanism for networks-on-chip of CMP
2011 (English)In: 2011 International Conference on Multimedia Technology, ICMT 2011, 2011, 2825-2828 p.Conference paper (Refereed)
As the size of CMOS technology scales down to nanometers domain, fault-tolerant is becoming a challenge for NoC. Turn model provides a simple and efficient systematic approach to the development of deadlock-free routing algorithms. In this paper, we propose a pseudo-receiving mechanism based on the support of local processor's cache to enable prohibited turn, and meanwhile make it keep deadlockfree. We present a fault-tolerant routing algorithm based on pseudo-receiving mechanism for 2D mesh. The routing algorithm is livelock-free in the cost of disable a few un-faulty links or nodes. The algorithm is applied to a single-cycle fixed output-buffered router. Experimental results show that, it achieves high performance even under high faulty rate.
Place, publisher, year, edition, pages
2011. 2825-2828 p.
, 2011 International Conference on Multimedia Technology, ICMT 2011
Chip multiprocessor, Fault-tolerant routing, Networks-on-chip, Turn model, CMOS technology, Deadlock-free routing, Fault tolerant routing, Fault-tolerant, Fault-tolerant routing algorithm, Networks on chips, Single cycle, Algorithms, CMOS integrated circuits, Microprocessor chips, Routers, Routing algorithms, Network architecture
IdentifiersURN: urn:nbn:se:kth:diva-150755DOI: 10.1109/ICMT.2011.6002067ScopusID: 2-s2.0-80052935124ISBN: 978-1-61284-771-9OAI: oai:DiVA.org:kth-150755DiVA: diva2:744929
2nd International Conference on Multimedia Technology, ICMT 2011, 26 July 2011 through 28 July 2011, Hangzhou
QC 201409092014-09-092014-09-092014-09-09Bibliographically approved