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Slice router: For fine-granularity fault-tolerant Networks-on-Chip
KTH, School of Information and Communication Technology (ICT), Electronic Systems.ORCID iD: 0000-0003-0061-3475
2011 (English)In: 2011 International Conference on Multimedia Technology, ICMT 2011, 2011, 3230-3233 p.Conference paper, Published paper (Refereed)
Abstract [en]

Almost all existing Networks-on-Chip (NoC) faulttolerant schemes are based on fault-tolerant routing algorithms. In these fault-tolerant schemes, faulty links or routers will be discarded all together. However, only a few part of the discarded link or router is faulty in most cases. It is wasteful to discard the whole link or router. In this paper, we present a slice router architecture which can be used in fine-granularity fault-tolerant NoC. The major motivation of presenting slice router is to refine faulty links and routers. The major idea is that a router is split into several sub-link routers, noted slices. Different from several physically independent routers, slices are coupled together in input/output ports. The coupling of slices makes the network to be able to fine-granularity fault-tolerant. In order to evaluate the fault-tolerant capability of slice routers, we design a looselycoupled 4-slices router with a backup sub-link in each link. Each slice is a single-cycle output buffered switch. Simulation results prove its fault-tolerant capability in the present of high faulty rates. The critical latency is only increased 0.04ns, because the configuration of slice interfaces is parallel with the output arbiter of slices. Under 65nm technology synthesized results show that, the increased area overhead of a slice router is only a few logic gates compared with the non-coupled slice router.

Place, publisher, year, edition, pages
2011. 3230-3233 p.
Series
2011 International Conference on Multimedia Technology, ICMT 2011
Keyword [en]
Fault-tolerant Routing, Networks-on-Chip, Reliability, Slice, 65nm technology, Area overhead, Fault tolerant routing, Fault-tolerant, Fault-tolerant capability, Fault-tolerant routing algorithm, Faulty links, Input/output, Networks on chips, Router architecture, Single cycle, Computer architecture, Network architecture, Routers
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-150753DOI: 10.1109/ICMT.2011.6001912Scopus ID: 2-s2.0-80052930556ISBN: 9781612847740 (print)OAI: oai:DiVA.org:kth-150753DiVA: diva2:744939
Conference
2nd International Conference on Multimedia Technology, ICMT 2011, 26 July 2011 through 28 July 2011, Hangzhou
Note

QC 20140909

Available from: 2014-09-09 Created: 2014-09-09 Last updated: 2014-09-09Bibliographically approved

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Lu, Zhonghai

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  • apa
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