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Impact of oxidation and reduction annealing on the electrical properties of Ge/La2O3/ZrO2 gate stacks
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.ORCID iD: 0000-0001-6705-1660
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.ORCID iD: 0000-0002-5845-3032
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2011 (English)In: European Solid-State Device Res. Conf., 2011, 75-78 p.Conference paper, Published paper (Refereed)
Abstract [en]

The current work is discussing the surface passivation of Germanium surfaces by using layered La2O3/ZrO2 high-k dielectrics deposited by Atomic Layer Deposition for use in Ge-based MOSFET devices. The improved electrical properties of these multilayered gate stacks exposed to oxidizing and reducing agencies in presence of thin Pt cap layers are investigated. The results suggest the formation of thin intermixed La xGeyOz interfacial layers with thicknesses controllable by oxidation time. An additional reduction treatment further improves the electrical properties of the gate dielectrics in contact to the Ge substrate. The scaling potential of the respective layered gate dielectrics used in MOS-based device structures is discussed. As a result low interface trap densities of the ALD deposited La2O3/ZrO2 layers on (100) Ge down to 3·1011 eV-1 cm -2 are demonstrated. A trade-off between improved interface trap density and equivalent oxide thickness is found.

Place, publisher, year, edition, pages
2011. 75-78 p.
Series
European Solid-State Device Research Conference, ISSN 1930-8876
Keyword [en]
Cap layers, Device structures, Equivalent oxide thickness, Gate stacks, Ge substrates, Germanium surface, High-k dielectric, Interface trap density, Interfacial layer, Multi-layered, Oxidation and reduction, Oxidation time, Reduction treatment, Surface passivation, Atomic layer deposition, Gate dielectrics, Germanium, Lanthanum oxides, Logic gates, MOSFET devices, Platinum, Solid state devices, Zirconium alloys, Electric properties
National Category
Materials Engineering
Identifiers
URN: urn:nbn:se:kth:diva-150653DOI: 10.1109/ESSDERC.2011.6044231Scopus ID: 2-s2.0-82955225068ISBN: 9781457707056 (print)OAI: oai:DiVA.org:kth-150653DiVA: diva2:746316
Conference
41st European Solid-State Device Research Conference, ESSDERC 2011, 12-16 September 2011, Helsinki, Finland
Note

QC 20140912

Available from: 2014-09-12 Created: 2014-09-08 Last updated: 2014-12-10Bibliographically approved

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Hellström, Per-Erik

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