Power characteristics of Asynchronous Networks-on-Chip
2011 (English)In: Int. Syst. Chip Conf., 2011, 160-165 p.Conference paper (Refereed)
Power characteristics of different Asynchronous Network on Chip (NoC) architectures are developed. Among different NoC architectures, the Butterfly Fat Tree (BFT) dissipates the minimum power. With increasing the number of IP blocks, the relative power consumption of the interconnects and the associate repeaters of the Asynchronous NoC architecture decreases as compared to the power consumption of the network switches. The power dissipation of the Asynchronous architecture is decreased by up to 57% as compared to the power dissipation of the conventional Synchronous architecture. The BFT is more efficient with increasing the number of IP blocks.
Place, publisher, year, edition, pages
2011. 160-165 p.
, International System on Chip Conference, ISSN 2164-1676
GALS, Interswitch Links, NoC, Power Dissipation, Asynchronous networks, IP block, Network switches, Networks on chips, NoC architectures, Power characteristic, Asynchronous sequential logic, Distributed computer systems, Energy dissipation, Microprocessor chips, Network architecture, Programmable logic controllers, Electric losses
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-150642DOI: 10.1109/SOCC.2011.6085125ISI: 000298082000035ScopusID: 2-s2.0-84255194465ISBN: 9781457716164OAI: oai:DiVA.org:kth-150642DiVA: diva2:746825
24th IEEE International System on Chip Conference, SOCC 2011, 26-28 September 2011, Taipei, Taiwan
QC 201409152014-09-152014-09-082014-09-15Bibliographically approved