Concept and design of exhaustive-parallel search algorithm for Network-on-Chip
2011 (English)In: Int. Syst. Chip Conf., 2011, 150-155 p.Conference paper (Refereed)
This paper presents the concept and design of exhaustive-parallel search algorithm for Network-on-Chip. The proposed parallel algorithm searches minimal path between source and destination in a forward-wave-propagation manner. The algorithm guarantees setup latency if the setup path exists. A high performance switch is designed to support exhaustive-parallel search algorithm. The NoC fabric is designed for 88 mesh architecture and its performance is evaluated.
Place, publisher, year, edition, pages
2011. 150-155 p.
, International System on Chip Conference, ISSN 2164-1676
Circuit-switch (CS), Exhaustive Parallel Search (EPS), Guaranteed Throughput (GT), Network-on-Chip (NoC), Guaranteed throughputs, High performance switches, Mesh architecture, Minimal path, Network on chip, Parallel search, Search Algorithms, Learning algorithms, Microprocessor chips, Servers, VLSI circuits, Programmable logic controllers
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-150641DOI: 10.1109/SOCC.2011.6085123ISI: 000298082000033ScopusID: 2-s2.0-84255175718ISBN: 9781457716164OAI: oai:DiVA.org:kth-150641DiVA: diva2:746841
24th IEEE International System on Chip Conference, SOCC 2011, 26-28 September 2011, Taipei, Taiwan
QC 201409152014-09-152014-09-082014-09-15Bibliographically approved