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Integrated logic synthesis using simulated annealing
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
KTH, School of Information and Communication Technology (ICT), Electronic Systems.ORCID iD: 0000-0001-7382-9408
Cadence Berkeley Labs, Berkeley, CA 94704, United States .
2011 (English)In: Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI, 2011, 407-410 p.Conference paper, Published paper (Refereed)
Abstract [en]

Conventional logic synthesis flows are composed of three separate phases: technology independent optimization, technology mapping, and technology dependent optimization. A fundamental problem with such a three-phased approach is that the global logic structure is decided during the first phase without any knowledge of the actual technology parameters considered during later phases. Although technology dependent optimization algorithms perform some limited logic restructuring, they cannot recover from fundamental mistakes made during the first phase, which often results in non-satisfiable solutions. In this paper, we present a method for integrating the three synthesis phases using an annealing algorithm as optimization framework. The annealing-based search is driven by a complex objective function, combining both technology independent as well as technology dependent optimization criteria. Our experimental results shown that, on average, the presented approach can improve the area and delay of circuits optimized with script rugged of SIS by 11.2% and 32.5% respectively.

Place, publisher, year, edition, pages
2011. 407-410 p.
Series
Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI
Keyword [en]
Rule-based optimization, Simulated annealing, Annealing algorithm, Fundamental problem, Logic restructuring, Logic structures, Logic synthesis, Objective functions, Optimization algorithms, Optimization criteria, Optimization framework, Technology independent, Technology mapping, Technology parameters, Algorithms, Delay circuits, Lakes, Technology
National Category
Computational Mathematics
Identifiers
URN: urn:nbn:se:kth:diva-151214DOI: 10.1145/1973009.1973095Scopus ID: 2-s2.0-79957755779ISBN: 9781450306676 (print)OAI: oai:DiVA.org:kth-151214DiVA: diva2:748347
Conference
21st Great Lakes Symposium on VLSI, GLSVLSI 2011, 2 May 2011 through 4 May 2011, Lausanne
Note

QC 20140919

Available from: 2014-09-19 Created: 2014-09-15 Last updated: 2014-09-19Bibliographically approved

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Dubrova, Elena

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CiteExportLink to record
Permanent link

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Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
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