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A gentle introduction to system verification
KTH, School of Information and Communication Technology (ICT), Computer and Systems Sciences, DSV.
2005 (English)In: New trends in software methodologies, tools and techniques, Amsterdam: IOS Press, 2005, 173-193 p.Conference paper, Published paper (Refereed)
Abstract [en]

Verification is an important instrument in the analysis of systems. Roughly, this means that requirements and designs are analyzed formally to determine their relationships. Various candidates for formalizing system development and integration have been proposed. However, a major obstacle is that these introduce non-standard objects and formalisms, leading to severe confusion. This is because these models often are unnecessarily complicated with several disadvantages regarding semantics as well as complexity. While avoiding the mathematical details as far as possible, we present some basic verification ideas using a simple language Such as predicate logic and demonstrate how this can be used for defining and analyzing static and dynamic requirement fulfillment by designs as well as for detecting conflicts. The formalities can be found in the appendix.

Place, publisher, year, edition, pages
Amsterdam: IOS Press, 2005. 173-193 p.
Series
Frontiers in Artificial Intelligence and Application, ISSN 0922-6389 ; Vol. 129
National Category
Software Engineering
Identifiers
URN: urn:nbn:se:kth:diva-148490ISI: 000273277600012Scopus ID: 2-s2.0-84860919891Libris ID: 10436285ISBN: 978-1-58603-556-3 (print)OAI: oai:DiVA.org:kth-148490DiVA: diva2:749941
Conference
4th International Conference on New Trends in Software Methodologies, Tools and Techniques, SoMeT_05; Tokyo; Japan; 28 September 2005 through 30 September 2005
Note

QC 20140925

Available from: 2014-09-25 Created: 2014-08-08 Last updated: 2014-09-25Bibliographically approved

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