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Concurrent chip package design for global clock distribution network using standing wave approach
KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
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2005 (English)Conference paper, Published paper (Refereed)
Abstract [en]

As a result of the continuous downscaling of CMOS technology, on chip frequency for high performance microprocessors will soon reach 10 GHz, according to the international technology roadmap for semiconductors (ITRS). A 10 GHz global clock distribution network using a standing wave approach is analyzed on the chip and package levels. On the chip level, a 10 GHz standing wave oscillator (SWO) for a global clock distribution network, using 0.18 /spl mu/m IP6M CMOS technology, is designed and analyzed. Simulation results show that skew is well controlled (about 1 ps), while the clock frequency variation is about 20% because power/ground return paths exist in different metal layers. On the package level, we assume that the chip size is 20/spl times/20 mm/sup 2/ and flip-chip bonding technology is used. Simulation results show that the skew at random positions of the transmission line (spiral or serpentine shape) is within 10% of /spl tau//sub clk/ when the attenuation is about 1.5 dB. For attenuation from 1.5 dB to 6.7 dB, the peak positions (n/spl lambda//2) can be used as clock nodes. For the mesh and plane shape, the skew is controlled within 10% of /spl tau//sub clk/ using the standing wave method.

Place, publisher, year, edition, pages
2005. 573-578 p.
Series
Proceedings - International Symposium on Quality Electronic Design, ISQED, ISSN 1948-3287
National Category
Computer Systems
Identifiers
URN: urn:nbn:se:kth:diva-148481DOI: 10.1109/ISQED.2005.33ISI: 000228486600094Scopus ID: 2-s2.0-84886709095ISBN: 9780769523019 (print)OAI: oai:DiVA.org:kth-148481DiVA: diva2:751019
Conference
6th International Symposium on Quality Electronic Design, ISQED 2005; San Jose, CA; United States; 21 March 2005 through 23 March 2005
Note

QC 20140930

Available from: 2014-09-30 Created: 2014-08-08 Last updated: 2017-03-24Bibliographically approved

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CiteExportLink to record
Permanent link

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Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf