Change search
ReferencesLink to record
Permanent link

Direct link
A time-spreading calibration technique for multi-bit/stage pipeline ADCs
KTH, School of Information and Communication Technology (ICT), Communication: Services and Infrastucture (Closed 20120101), Communication Systems, CoS (closed 2012-01-01). Fudan University, China.
KTH, School of Information and Communication Technology (ICT), Communication: Services and Infrastucture (Closed 20120101), Communication Systems, CoS (closed 2012-01-01).
2009 (English)In: 2009 International SoC Design Conference, ISOCC 2009, 2009, 416-419 p.Conference paper (Refereed)
Abstract [en]

This paper describes a robust and effective calibration algorithm for pipelined analog-to-digital converters, which compensates for large gain errors, without the requirement for a long startup time as required by the other dither-based algorithms presented in literature. The proposed technique, time-spreading self-calibration, operates the front-end sample-and-hold stage in half rate at startup and cancels out the strong input-interference by using subtractive correlation, achieves a quick convergence. When the sample-and-hold stage operates in full rate as normal, the algorithm works as a background dither-based scheme and enables to calibrate time-variant gain errors. Simulation results show that it only needs wake-up time of 3 × 10 5·T s to correct a 15-bit pipelined ADC in the presence of realistic capacitor mismatch and finite op-amp gain, where T s is the sampling period.

Place, publisher, year, edition, pages
2009. 416-419 p.
Keyword [en]
Calibration algorithm, Calibration techniques, Capacitor mismatch, Full rate, Gain errors, Half-rate, Pipeline ADCs, Pipelined ADCs, Pipelined analog-to-digital converter, Sample-and-hold, Sampling period, Self calibration, Simulation result, Startup time, Time-spreading, Time-variant gains, Up time, Calibration, Errors, Multicarrier modulation, Programmable logic controllers, Analog to digital conversion
National Category
Communication Systems
URN: urn:nbn:se:kth:diva-152388DOI: 10.1109/SOCDC.2009.5423867ScopusID: 2-s2.0-77951430286ISBN: 978-142445034-3OAI: diva2:751451
2009 International SoC Design Conference, ISOCC 2009, 22 November 2009 through 24 November 2009, Busan, China

QC 20141001

Available from: 2014-10-01 Created: 2014-09-26 Last updated: 2016-01-27Bibliographically approved
In thesis
1. Low Power Analog Interface Circuits toward Software Defined Sensors
Open this publication in new window or tab >>Low Power Analog Interface Circuits toward Software Defined Sensors
2016 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

Internet of Things is expanding to the areas such as healthcare, home management, industrial, agriculture, and becoming pervasive in our life, resulting in improved efficiency, accuracy and economic benefits. Smart sensors with embedded interfacing integrated circuits (ICs) are important enablers, hence, variety of smart sensors are required. However, each type of sensor requires specific interfacing chips, which divides the huge market of sensors’ interface chips into lots of niche markets, resulting in high develop cost and long time-to-market period for each type. Software defined sensor is regarded as a promising solution, which is expected to use a flexible interface platform to cover different sensors, deliver specificity through software programming, and integrate easily into the Internet of Things. In this work, research is carried out on the design and implementations of ultra low power analog interface circuits toward software defined sensors for healthcare services based on Internet of Things.

   This thesis first explores architectures and circuit techniques for energy-efficient and flexible analog to digital conversion. A time-spreading digital calibration, to calibrate the errors due to finite gain and capacitor mismatch in multi-bit/stage pipelined converters, is developed with short convergence time. The effectiveness of the proposed technique is demonstrated with intensive simulations. Two novel circuit level techniques, which can be combined with digital calibration techniques to further improve the energy efficiency of the converters, are also presented. One is the Common-Mode-Sensing-and-Input-Interchanging (CSII) operational-transconductance-amplifier (OTA) sharing technique to enable eliminating potential memory effects. The other is a workload-balanced multiplying digital-to-analog converter (MDAC) architecture to improve the settling efficiency of a high linear multi-bit stage. Two prototype converters have been designed and fabricated in 0.13 μm CMOS technology. The first one is a 14 bit 50 MS/s digital calibrated pipelined analog to digital converter that employs the workload-balanced MDAC architecture and time-spreading digital calibration technique to achieve improved power-linearity tradeoff. The second one is a 1.2 V 12 bit 5~45 MS/s speed and power-scalable ADC incorporating the CSII OTA-sharing technique, sample-and-hold-amplifier-free topology and adjustable current bias of the building blocks to minimize the power consumption. The detailed measurement results of both converters are reported and deliver the experimental verification of the proposed techniques.

    Secondly, this research investigates ultra-low-power analog front-end circuits providing programmability and being suitable for different types of sensors. A pulse-width- -modulation-based architecture with a folded reference is proposed and proven in a 0.18 μm technology to achieve high sensitivity and enlarged dynamic range when sensing the weak current signals. A 8-channel bio-electric sensing front-end, fabricated in a 0.35 μm CMOS technology is also presented that achieves an input impedance of 1 GΩ, input referred noise of 0.97 Vrms and common mode rejection ratio of 114 dB. With the programmable gain and cut-off frequency, the front-end can be configured to monitor for long-term a variety of bio-electric signals, such as electrooculogram (EOG), electromyogram (EMG), electroencephalogram (EEG) and electrocardiogram (ECG) signals. The proposed front-end is integrated with dry electrodes, a microprocessor and wireless link to build a battery powered E-patch for long-term and continuous monitoring. In-vivo test results with dry electrodes in the field trials of sitting, standing, walking and running slowly, show that the quality of ECG signal sensed by the E-patch satisfies the requirements for preventive cardiac care.

   Finally, a wireless multimodal bio-electric sensor system is presented. Enabled by a customized flexible mixed-signal system on chip (SoC), this bio-electric sensor system is able to be configured for ECG/EMG/EEG recording, bio-impedance sensing, weak current stimulation, and other promising functions with biofeedback. The customized SoC, fabricated in a 0.18 μm CMOS technology, integrates a tunable analog front-end, a 10 bit ADC, a 14 bit sigma-delta digital to current converter, a 12 bit digital to voltage converter, a digital accelerator for wavelet transformation and data compression, and a serial communication protocol. Measurement results indicate that the SoC could support the versatile bio-electric sensor to operate in various applications according to specific requirements.

Place, publisher, year, edition, pages
Stockholm: KTH Royal Institute of Technology, 2016. xv, 135 p.
, TRITA-ICT, ISSN 2015:25
IoT, software defined sensor, SoC, bio-medical electronics, bio-electric sensor, E-patch, wearable sensor, wearable healthcare system, pervasive healthcare, CMOS, ADC, digital calibration, analog front-end, folded reference.
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Electrical Engineering
urn:nbn:se:kth:diva-179671 (URN)978-91-7595-779-1 (ISBN)
Public defence
2016-01-21, Sal A, Electrum, Electrum 229, Kista, 13:30 (English)

QC 20151221

Available from: 2015-12-21 Created: 2015-12-18 Last updated: 2016-01-20Bibliographically approved

Open Access in DiVA

No full text

Other links

Publisher's full textScopus

Search in DiVA

By author/editor
Qin, YajieSignell, Svante
By organisation
Communication Systems, CoS (closed 2012-01-01)
Communication Systems

Search outside of DiVA

GoogleGoogle Scholar
The number of downloads is the sum of all downloads of full texts. It may include eg previous versions that are now no longer available

Altmetric score

Total: 38 hits
ReferencesLink to record
Permanent link

Direct link