A time-spreading calibration technique for multi-bit/stage pipeline ADCs
2009 (English)In: 2009 International SoC Design Conference, ISOCC 2009, 2009, 416-419 p.Conference paper (Refereed)
This paper describes a robust and effective calibration algorithm for pipelined analog-to-digital converters, which compensates for large gain errors, without the requirement for a long startup time as required by the other dither-based algorithms presented in literature. The proposed technique, time-spreading self-calibration, operates the front-end sample-and-hold stage in half rate at startup and cancels out the strong input-interference by using subtractive correlation, achieves a quick convergence. When the sample-and-hold stage operates in full rate as normal, the algorithm works as a background dither-based scheme and enables to calibrate time-variant gain errors. Simulation results show that it only needs wake-up time of 3 × 10 5·T s to correct a 15-bit pipelined ADC in the presence of realistic capacitor mismatch and finite op-amp gain, where T s is the sampling period.
Place, publisher, year, edition, pages
2009. 416-419 p.
Calibration algorithm, Calibration techniques, Capacitor mismatch, Full rate, Gain errors, Half-rate, Pipeline ADCs, Pipelined ADCs, Pipelined analog-to-digital converter, Sample-and-hold, Sampling period, Self calibration, Simulation result, Startup time, Time-spreading, Time-variant gains, Up time, Calibration, Errors, Multicarrier modulation, Programmable logic controllers, Analog to digital conversion
IdentifiersURN: urn:nbn:se:kth:diva-152388DOI: 10.1109/SOCDC.2009.5423867ScopusID: 2-s2.0-77951430286ISBN: 978-142445034-3OAI: oai:DiVA.org:kth-152388DiVA: diva2:751451
2009 International SoC Design Conference, ISOCC 2009, 22 November 2009 through 24 November 2009, Busan, China
QC 201410012014-10-012014-09-262016-01-27Bibliographically approved