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High throughput architecture for OCTAGON network on chip
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. Ohio State University, United States . (RaMSiS Group)
2009 (English)In: 2009 16th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2009, IEEE , 2009, 101-104 p.Conference paper, Published paper (Refereed)
Abstract [en]

High Throughput Octagon architecture to achieve high performance Networks on Chip (NoC) is proposed. The architecture increase. The throughput oy the network by 17% while preservin. The average latency. The area of High Throughput OCTAGON switch is decreased by 18% as compared to OCTAGON switch. The total metal resources required to implement High Throughput OCTAGON design is increased by 8% as compared to the total metal resources required to implement OCTAGON design. The extra power consumption required to achiev. The proposed architecture is 2% oy the total power consumption oy the OCTAGON architecture.

Place, publisher, year, edition, pages
IEEE , 2009. 101-104 p.
Keyword [en]
Latency, Noc, OCTAGON, Throughput
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-152414DOI: 10.1109/ICECS.2009.5410933Scopus ID: 2-s2.0-77951459701ISBN: 978-142445091-6 (print)OAI: oai:DiVA.org:kth-152414DiVA: diva2:752010
Conference
2009 16th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2009, 13 December 2009 through 16 December 2009, Yasmine Hammamet, Tunisia
Note

QC 20141002

Available from: 2014-10-02 Created: 2014-09-26 Last updated: 2014-10-02Bibliographically approved

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CiteExportLink to record
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