High throughput architecture for OCTAGON network on chip
2009 (English)In: 2009 16th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2009, IEEE , 2009, 101-104 p.Conference paper (Refereed)
High Throughput Octagon architecture to achieve high performance Networks on Chip (NoC) is proposed. The architecture increase. The throughput oy the network by 17% while preservin. The average latency. The area of High Throughput OCTAGON switch is decreased by 18% as compared to OCTAGON switch. The total metal resources required to implement High Throughput OCTAGON design is increased by 8% as compared to the total metal resources required to implement OCTAGON design. The extra power consumption required to achiev. The proposed architecture is 2% oy the total power consumption oy the OCTAGON architecture.
Place, publisher, year, edition, pages
IEEE , 2009. 101-104 p.
Latency, Noc, OCTAGON, Throughput
Other Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-152414DOI: 10.1109/ICECS.2009.5410933ScopusID: 2-s2.0-77951459701ISBN: 978-142445091-6OAI: oai:DiVA.org:kth-152414DiVA: diva2:752010
2009 16th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2009, 13 December 2009 through 16 December 2009, Yasmine Hammamet, Tunisia
QC 201410022014-10-022014-09-262014-10-02Bibliographically approved