Design of a novel capacitorless DRAM cell with enhanced retention performance
2009 (English)In: 2009 IEEE Workshop on Microelectronics and Electron Devices (WMED), IEEE , 2009, 41-44 p.Conference paper (Refereed)
A novel capacitorless DRAM cell with enhanced retention performance is investigated. The write / read mechanisms, speed, retention performance are studied with numerical simulations. Further, the manufacturing method of this device is briefly discussed.
Place, publisher, year, edition, pages
IEEE , 2009. 41-44 p.
Capacitorless, Dynamic random access memory, Floating, Floating junction, Retention
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-153593DOI: 10.1109/WMED.2009.4816144ISI: 000266868800007ScopusID: 2-s2.0-67650118255ISBN: 978-142443552-4OAI: oai:DiVA.org:kth-153593DiVA: diva2:753101
2009 IEEE Workshop on Microelectronics and Electron Devices, WMED 2009, 3 April 2009 through 3 April 2009, Boise, ID, United States
QC 201410072014-10-072014-10-062014-10-07Bibliographically approved