High throughput architecture for high performance NoC
2009 (English)In: ISCAS: 2009 IEEE International Symposium on Circuits and Systems, IEEE , 2009, 2241-2244 p.Conference paper (Refereed)
High Throughput Butterfly Fat Tree (HTBFT) architecture to achieve high performance Networks on Chip (NoC) is proposed. The architecture increases the throughput of the network by 38% while preserving the average latency. The area of HTBFT switch is decreased by 18% as compared to Butterfly Fat Tree switch. The total metal resources required to implement HTBFT design is increased by 5% as compared to the total metal resources required to implement BFT design. The extra power consumption required to achieve the proposed architecture is 3% of the total power consumption of the BFT architecture.
Place, publisher, year, edition, pages
IEEE , 2009. 2241-2244 p.
, Proceedings - IEEE International Symposium on Circuits and Systems, ISSN 0271-4310
BFT, Latency, NoC, Throughput
Computer Science Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-153565DOI: 10.1109/ISCAS.2009.5118244ISI: 000275929801247ScopusID: 2-s2.0-70350165397ISBN: 978-142443828-0OAI: oai:DiVA.org:kth-153565DiVA: diva2:754953
2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009, 24 May 2009 through 27 May 2009, Taipei, Taiwan
QC 201410132014-10-132014-10-062014-10-13Bibliographically approved