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High throughput architecture for CLICHÉ network on chip
KTH, School of Information and Communication Technology (ICT), Electronic Systems. ((RaMSiS Group))
2009 (English)In: Proceedings - IEEE International SOC Conference, SOCC 2009, 2009, 155-158 p.Conference paper, Published paper (Refereed)
Abstract [en]

High Throughput Chip-Level Integration of Communicating Heterogeneous Elements (CLICHÉ) architecture to achieve high performance Networks on Chip (NoC) is proposed. The architecture increases the throughput of the network by 40% while preserving the average latency. The area of High Throughput CLICHÉ switch is decreased by 18% as compared to CLICHÉ switch. The total metal resources required to implement High Throughput CLICHÉ design is increased by 7% as compared to the total metal resources required to implement CLICHÉ design. The extra power consumption required to achieve the proposed architecture is 8% of the total power consumption of the CLICHÉ architecture.

Place, publisher, year, edition, pages
2009. 155-158 p.
Keyword [en]
CLICHÉ, Latency, NoC, Throughput
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-152757DOI: 10.1109/SOCCON.2009.5398069ISI: 000277503200032Scopus ID: 2-s2.0-77949581774ISBN: 978-142445220-0 (print)OAI: oai:DiVA.org:kth-152757DiVA: diva2:755203
Conference
IEEE International SOC Conference, SOCC 2009, 9 September 2009 through 11 September 2009, Belfast, Ireland
Note

QC 20141014

Available from: 2014-10-14 Created: 2014-10-01 Last updated: 2014-10-14Bibliographically approved

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