Power efficient networks on chip
2009 (English)In: 2009 16th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2009, 2009, 105-108 p.Conference paper (Refereed)
a low power switch design is proposed to achieve power-efficient Network on Chip (NoC). The proposed NoC switch reduce. The power consumption oy the Butterfly Fat Tree (BFT) architecture by 28 % as compared to the conventional BFT switch. Moreover. The power reduction technique is applied to different NoC architectures. The technique reduce. The power consumption oy the network by up to 41%. Whe. The power consumption oy the whole network includin. The interswich links and repeaters is taken into account. The overall power consumption is decreased by up to 33% at the maximum operating frequency oy the switch. The BFT architecture consume. The minimum power as compared to other NoC architectures.
Place, publisher, year, edition, pages
2009. 105-108 p.
BFT, Interswitch links, Leakage power, Noc
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-152375DOI: 10.1109/ICECS.2009.5410930ScopusID: 2-s2.0-77951466147ISBN: 978-142445091-6OAI: oai:DiVA.org:kth-152375DiVA: diva2:755318
2009 16th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2009, 13 December 2009 through 16 December 2009, Yasmine Hammamet, Tunisia
QC 201410142014-10-142014-09-262014-10-14Bibliographically approved