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Power efficient networks on chip
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
2009 (English)In: 2009 16th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2009, 2009, 105-108 p.Conference paper, Published paper (Refereed)
Abstract [en]

a low power switch design is proposed to achieve power-efficient Network on Chip (NoC). The proposed NoC switch reduce. The power consumption oy the Butterfly Fat Tree (BFT) architecture by 28 % as compared to the conventional BFT switch. Moreover. The power reduction technique is applied to different NoC architectures. The technique reduce. The power consumption oy the network by up to 41%. Whe. The power consumption oy the whole network includin. The interswich links and repeaters is taken into account. The overall power consumption is decreased by up to 33% at the maximum operating frequency oy the switch. The BFT architecture consume. The minimum power as compared to other NoC architectures.

Place, publisher, year, edition, pages
2009. 105-108 p.
Keyword [en]
BFT, Interswitch links, Leakage power, Noc
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-152375DOI: 10.1109/ICECS.2009.5410930Scopus ID: 2-s2.0-77951466147ISBN: 978-142445091-6 (print)OAI: oai:DiVA.org:kth-152375DiVA: diva2:755318
Conference
2009 16th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2009, 13 December 2009 through 16 December 2009, Yasmine Hammamet, Tunisia
Note

QC 20141014

Available from: 2014-10-14 Created: 2014-09-26 Last updated: 2014-10-14Bibliographically approved

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