High throughput high performance NoC switch
2008 (English)Conference paper (Refereed)
Increasing the number of virtual channels can improve the throughput in an on-chip interconnection network. High Throughput Butterfly Fat Tree (HTBFT) architecture to achieve high performance Networks on Chip (NoC) is proposed. The architecture increases the throughput of the network by 38% while preserving the average latency. The area of HTBFT switch is decreased by 18% as compared to Butterfly Fat Tree switch.
Place, publisher, year, edition, pages
2008. 237-240 p.
, Norchip - 26th Norchip Conference, Formal Proceedings
BFT, Latency, NoC, Throughput, Electric network topology, Interconnection networks, High performance networks, High throughputs, NoC switches, On-chip interconnection networks, Virtual channels
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-154127DOI: 10.1109/NORCHP.2008.4738319ScopusID: 2-s2.0-62949211750ISBN: 9781424424931OAI: oai:DiVA.org:kth-154127DiVA: diva2:757528
26th Norchip Conference, Norchip; Tallinn; Estonia; 17 November 2008 through 18 November 2008
QC 201410222014-10-222014-10-142014-10-22Bibliographically approved