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High throughput high performance NoC switch
KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT. Electrical Engineering Dept., Ohio State University, United States . (RaMSiS Group)
2008 (English)Conference paper, Published paper (Refereed)
Abstract [en]

Increasing the number of virtual channels can improve the throughput in an on-chip interconnection network. High Throughput Butterfly Fat Tree (HTBFT) architecture to achieve high performance Networks on Chip (NoC) is proposed. The architecture increases the throughput of the network by 38% while preserving the average latency. The area of HTBFT switch is decreased by 18% as compared to Butterfly Fat Tree switch.

Place, publisher, year, edition, pages
2008. 237-240 p.
Series
Norchip - 26th Norchip Conference, Formal Proceedings
Keyword [en]
BFT, Latency, NoC, Throughput, Electric network topology, Interconnection networks, High performance networks, High throughputs, NoC switches, On-chip interconnection networks, Virtual channels
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-154127DOI: 10.1109/NORCHP.2008.4738319Scopus ID: 2-s2.0-62949211750ISBN: 9781424424931 (print)OAI: oai:DiVA.org:kth-154127DiVA: diva2:757528
Conference
26th Norchip Conference, Norchip; Tallinn; Estonia; 17 November 2008 through 18 November 2008
Note

QC 20141022

Available from: 2014-10-22 Created: 2014-10-14 Last updated: 2014-10-22Bibliographically approved

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Ismail, Muhammed
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