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Survey on Combinatorial Register Allocation and Instruction Scheduling
KTH, School of Information and Communication Technology (ICT), Software and Computer systems, SCS. SICS (Swedish Institute of Computer Science) and KTH (Royal Institute of Technology).ORCID iD: 0000-0002-2806-7333
KTH, School of Information and Communication Technology (ICT), Software and Computer systems, SCS.ORCID iD: 0000-0002-6283-7004
2014 (English)Report (Other academic)
Abstract [en]

Register allocation and instruction scheduling are two central compiler back-end problems that are critical for quality. In the last two decades, combinatorial optimization has emerged as an alternative approach to traditional, heuristic algorithms for these problems. Combinatorial approaches are generally slower but more flexible than their heuristic counterparts and have the potential to generate optimal code. This paper surveys existing literature on combinatorial register allocation and instruction scheduling. The survey covers approaches that solve each problem in isolation as well as approaches that integrate both problems. The latter have the potential to generate code that is globally optimal by capturing the trade-off between conflicting register allocation and instruction scheduling decisions.

Place, publisher, year, edition, pages
2014.
National Category
Computer Systems
Research subject
Computer Science
Identifiers
URN: urn:nbn:se:kth:diva-154598OAI: oai:DiVA.org:kth-154598DiVA: diva2:758112
Funder
Vinnova, VR 621-2011-6229
Note

QC 20141117.

Archived at: arXiv:1409.7628 [cs.PL]

Available from: 2014-10-24 Created: 2014-10-24 Last updated: 2014-11-17Bibliographically approved
In thesis
1. Integrated Register Allocation and Instruction Scheduling with Constraint Programming
Open this publication in new window or tab >>Integrated Register Allocation and Instruction Scheduling with Constraint Programming
2014 (English)Licentiate thesis, comprehensive summary (Other academic)
Abstract [en]

This dissertation proposes a combinatorial model, program representations, and constraint solving techniques for integrated register allocation and instruction scheduling in compiler back-ends. In contrast to traditional compilers based on heuristics, the proposed approach generates potentially optimal code by considering all trade-offs between interdependent decisions as a single optimization problem.

The combinatorial model is the first to handle a wide array of global register allocation subtasks, including spill code optimization, ultimate coalescing, register packing, and register bank assignment, as well as instruction scheduling for Very Long Instruction Word (VLIW) processors. The model is based on three novel, complementary program representations: Linear Static Single Assignment for global register allocation; copy extension for spilling, basic coalescing, and register bank assignment; and alternative temporaries for spill code optimization and ultimate coalescing. Solving techniques are proposed that exploit the program representation properties for scalability.

The model, program representations, and solving techniques are implemented in Unison, a code generator that delivers potentially optimal code while scaling to medium-size functions. Thorough experiments show that Unison: generates faster code (up to 41% with a mean improvement of 7%) than LLVM (a state-of-the-art compiler) for Hexagon (a challenging VLIW processor), generates code that is competitive with LLVM for MIPS32 (a simpler RISC processor), is robust across different benchmarks such as MediaBench and SPECint 2006, scales up to medium-size functions of up to 1000 instructions, and adapts easily to different optimization criteria.

The contributions of this dissertation are significant. They lead to a combinatorial approach for integrated register allocation and instruction scheduling that is, for the first time, practical (it robustly scales to medium-size functions) and effective (it yields better code than traditional heuristic approaches).

Place, publisher, year, edition, pages
Stockholm, Sweden: KTH Royal Institute of Technology, 2014. 48 p.
Series
TRITA-ICT-ECS AVH, ISSN 1653-6363 ; 14:13
National Category
Computer Science
Research subject
Computer Science
Identifiers
urn:nbn:se:kth:diva-154599 (URN)978-91-7595-311-3 (ISBN)
Presentation
2014-11-27, Sal A, Electrum, Kistagången 16, Kista, Stockholm, 14:00 (English)
Opponent
Supervisors
Note

QC 20141117

Available from: 2014-11-17 Created: 2014-10-24 Last updated: 2014-11-17Bibliographically approved

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Castañeda Lozano, RobertoSchulte, Christian

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