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Power-supply noise attributed timing jitter in nonoverlapping clock generation circuits
KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
2006 (English)Conference paper (Refereed)
Abstract [en]

This work describes an analysis of timing jitter induced by power-supply noise in nonoverlapping clock generation circuits typically used in switched-capacitor sigma-delta modulators. Substrate noise effects are also included but not treated as a separate phenomenon since the MOSFET bulk contacts are connected to the power-supply or ground. Two different nonoverlapping clock generation circuits have been compared and treated independently: the NOR based and the NAND based architectures. Furthermore, all possible connection topologies of the circuit blocks in the clock generation circuits are investigated. Monte Carlo simulations have been performed in Spectre at BSIM3v3 transistor model level using parameters from a 0.18μm process to show which of the topologies is most suitable as clock generator for wideband applications. In terms of timing jitter sensitivity to power-supply noise, the NOR based architecture is slightly more robust and suitable for providing a timing reference to a sampling circuit.

Place, publisher, year, edition, pages
2006. 43-46 p.
, 2006 IEEE Dallas/CAS Workshop onDesign, Applications, Integration and Software, DCAS-06
Keyword [en]
Clocks, Cosmic ray detectors, Delta sigma modulation, Electric currents, Energy storage, Jitter, Modulators, Monte Carlo methods, Networks (circuits), Power generation, Radio receivers, Sensitivity analysis, Software design, Time measurement, Timing jitter, Topology, (e, 3e) process, Circuit blocks, Clock generation circuits, clock generators, Monte Carlo Simulation (MCS), Power supplies, Power-supply noise, sampling circuits, Sigma delta modulator (SDM), Spectre (CO), Substrate noise effects, Switched capacitor (SC), Timing reference (TR), Transistor modeling, Wide band applications, Timing circuits
National Category
Computer Systems
URN: urn:nbn:se:kth:diva-155423DOI: 10.1109/DCAS.2006.321029ScopusID: 2-s2.0-44949161547ISBN: 1424406692ISBN: 9781424406692OAI: diva2:762420
2006 IEEE Dallas ICAS Workshop on Design, Applications, Integration and Software, DCAS-06; Richardson, TX; United States; 29 October 2006 through 30 October 2006

QC 20141111

Available from: 2014-11-11 Created: 2014-11-05 Last updated: 2014-11-11Bibliographically approved

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ReferencesLink to record
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