Change search
ReferencesLink to record
Permanent link

Direct link
A Fair and Maximal Allocator for Single-Cycle On-Chip Homogeneous Resource Allocation
KTH, School of Information and Communication Technology (ICT), Electronic Systems.ORCID iD: 0000-0001-7966-6128
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
KTH, School of Information and Communication Technology (ICT), Electronic Systems.ORCID iD: 0000-0003-0061-3475
2014 (English)In: IEEE Transactions on Very Large Scale Integration (vlsi) Systems, ISSN 1063-8210, Vol. 23, no 10, 2229-2233 p.Article in journal (Refereed) Published
Abstract [en]

Traditional allocators for network-on-chip (NoC) routers suffer from either poor-matching quality or limited fairness. We propose a waterfall (WTF) allocator targeting homogeneous resource allocation, which provides single-cycle maximal matching while guaranteeing strong fairness based on the round-robin principle. It can be implemented with a loop-free structure. In 90 nm technology, the allocator operates at about 1 GHz clock frequency. We compare WTF with wave-front, separable-input-first, and separable-output-first allocators and find that it is at least 10% smaller, has 50% less delay under high load, and uses 3% less power than any of these alternatives. Also, WTF is at least as fair or clearly fairer. We also find that in a 4 x 4 circuit switched NoC the use of WTF gives up to 20% higher network performance.

Place, publisher, year, edition, pages
2014. Vol. 23, no 10, 2229-2233 p.
Keyword [en]
Allocator, fairness, maximal matching, network-on-chip (NoC), round-robin
National Category
Computer Science
URN: urn:nbn:se:kth:diva-155469DOI: 10.1109/TVLSI.2013.2284563ISI: 000343014100020ScopusID: 2-s2.0-84907660701OAI: diva2:762584

QC 20141112

Available from: 2014-11-12 Created: 2014-11-06 Last updated: 2015-11-09Bibliographically approved
In thesis
1. New circuit switching techniques in on-chip networks
Open this publication in new window or tab >>New circuit switching techniques in on-chip networks
2015 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

Network on Chip (NoC) is proposed as a promising technology to address the communication challenges in deep sub-micron era. NoC brings network-based communication into the on-chip environment and tackles the problems like long wire complexities, bandwidth scaling and so on. After more than a decade's evolution and development, there are many NoC architectures and solutions available. Nevertheless, NoCs can be classi_ed into two categories: packet switched NoC and circuit switched NoC. In this thesis, targeting circuit switched NoC, we present our innovations and considerations on circuit switched NoCs in three areas, namely, connection setup method, time division multiplexing (TDM) technology and spatial division multiplexing (SDM) technology.

Connection setup technique deeply inuences the architecture and performance of a circuit switched NoC, since circuit switched NoC requires to set up connections before launching data transfer. We propose a novel parallel probe based method for dynamic distributed connection setup. This setup method on one hand searches all the possible minimal paths in parallel. On the other hand, it also has a mechanism to reduce resource occupation during the path search process by reclaiming redundant paths. With this setup method, connections are more likely to be established because of the exploration on the path diversity.

TDM based NoC constitutes a sub-category of circuit switched NoC. We propose a double time-wheel technique to facilitate a probe based connection setup in TDM NoCs. With this technique, path search algorithms used in connection setup are no longer limited to deterministic routing algorithms. Moreover, the hardware cost can be reduced, since setup requests and data flows can co-exist in one network. Apart from the double time-wheel technique for connection setup, we also propose a highway technique that can enhance the slot utilization during data transfer. This technique can accelerate the transfer of a data flow while maintaining the throughput guarantee and the packet order.

SDM based NoC constitutes another sub-category of circuit switched NoC. SDM NoC can benefit from high clock frequency and simple synchronization efforts. To better support the dynamic connection setup in SDM NoCs, we design a single cycle allocator for channel allocation inside each router. This allocator can guarantee both strong fairness and maximal matching quality. We also build up a circuit switched NoC, which can support multiple channels and multiple networks, to study different ways of organizing channels and setting up connections. Finally, we make a comparison between circuit switched NoC and packet switched NoC. We show the strengths and weaknesses on each of them by analysis and evaluation.

Place, publisher, year, edition, pages
Stockholm: KTH Royal Institute of Technology, 2015. xvi, 82 p.
TRITA-ICT-ECS AVH, ISSN 1653-6363 ; 2015:18
National Category
Computer Systems
urn:nbn:se:kth:diva-176624 (URN)978-91-7595-727-2 (ISBN)
Public defence
2015-12-04, Sal A, Elektrum, KTH-ICT, Kista, 09:00 (English)

QC 20151109

Available from: 2015-11-09 Created: 2015-11-09 Last updated: 2015-11-09Bibliographically approved

Open Access in DiVA

No full text

Other links

Publisher's full textScopus

Search in DiVA

By author/editor
Liu, ShaotengJantsch, AxelLu, Zhonghai
By organisation
Electronic Systems
In the same journal
IEEE Transactions on Very Large Scale Integration (vlsi) Systems
Computer Science

Search outside of DiVA

GoogleGoogle Scholar
The number of downloads is the sum of all downloads of full texts. It may include eg previous versions that are now no longer available

Altmetric score

Total: 93 hits
ReferencesLink to record
Permanent link

Direct link