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Managing the Complexity in Embedded and Cyber-Physical System Design: System Modeling and Design-Space Exploration
KTH, School of Information and Communication Technology (ICT), Electronic Systems.ORCID iD: 0000-0002-2171-1528
2014 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

To cope with the increasing complexity of embedded and cyber-physical system design, different system-level design approaches are proposed which start from abstract models and implement them using design flows with high degrees of automation. However, creating models of such systems and also formulating the mathematical problems arising in these design flows are themselves challenging tasks. A promising approach is the composable construction of these models and problems from more basic entities. Unfortunately, it is non-trivial to propose such compositional formulations today because the current practice in the electronic design automation domain tends to be on using imperative languages and frameworks due to legacy and performance-oriented reasons.

This thesis addresses the system design complexity by first promoting proper formalisms and frameworks for capturing models and formulating design-space exploration problems for electronic system-level design in a declarative style; and second, propose realizations based on the industrially accepted languages and frameworks which hold the interesting properties such as composability and parallelism.

For modeling, ForSyDe, a denotational system-level modeling formalism for heterogeneous embedded systems is chosen, extended with timed domains to make it more appropriate for capturing cyber-physical systems, and mapped on top of the IEEE standard system design language SystemC. The realized modeling framework, called ForSyDe-SystemC, can be used for modeling systems of heterogeneous nature and their composition to form more sophisticated systems and also conducting parallel and distributed simulation for boosting the simulation speed. Another extension to ForSyDe, named wrapper processes, introduces the ability to compose formal ForSyDe models with legacy IP blocks running in external execution environments to perform a heterogeneous co-simulation.

In platform-based design flows, the correct and optimal mapping of an application model onto a flexible platform involves solving a hard problem, named design space exploration. This work proposes Tahmuras, a constraint- based framework to construct generic design space exploration problems as the composition of three individual sub-problems: the application, the platform, and the mapping and scheduling problems. In this way, the model of the design space exploration problem in Tahmuras is automatically generated for each combination of application semantics, target platform, and mapping and scheduling policy simply by composing their respective problems. Using constraint programming, problems can be modeled in a declarative style, while they can be solved in a variety of different styles, including imperative solving heuristics commonly used to solve difficult problems. Efficient parallel solvers exists for constraint programming. 

Abstract [sv]

Den ökande komplexiteten är en stor utmaning för konstruktionen av framtida inbyggda system. För att möta utmaningen utvecklas nu konstruktionsmetoder som har som mål att starta från en abstrakt modell och att generera en implementering genom ett konstruktionsflöde med hög automatiseringsgrad. Dessvärre är dock skapandet av abstrakta systemmodeller och formaliseringen av de relaterade matematiska problemen i sig ett mycket utmanande problem. Konstruktion genom komposition av basenheter är en lovande idé, men tyvärr är det väldigt svårt att introducera metoden i dagens industriella konstruktionsflöden på grund av imperativa programmeringsspråk och ett gammalt arv i form av existerande kodbas och äldre konstruktioner.

Avhandlingen adresserar komplexiten inom systemkonstruktion genom att föreslå passande formalismer för att uttrycka modeller i en deklarativ stil och angripa problemet att hitta en passande implementering. Dessutom visar avhandlingen hur dessa formalismer kan realiseras i en form som kan användas i ett industriellt sammanhang utan att förlora formalismens viktiga grundläggande egenskaper som komposition och parallelism.

Modelleringen använder och utökar ForSyDe, en konstruktionsmetod för heterogena inbyggda system. Tilläggen består av en modelleringsmodell som kan fånga specifika egenskaper hos heterogena inbyggda system, samt en implementering av ForSyDe i SystemC, ett industriellt modelleringsspråk som är standardiserat av IEEE. Den nya utvecklingsmiljön, ForSyDe-SystemC, kan användas för att modellera inbyggda system, komponera systemmodeller till större system, samt möjliggör genomförandet av parallella och distribuerade simuleringar med medföljande hög simuleringshastighet. Avhandlingen introducerar också “wrapper”-konceptet i ForSyDe som möjliggör integrationen av existerande modeller och system som en del av en formell ForSyDe-modell och deras co-simulering. ForSyDe-SystemC har använts inom EU-projekt av industriella partner för modellering av egna system.

Att hitta en korrekt och effektiv implementering av en abstrakt systemmodell är målet inom aktiviteten “design space exploration” (DSE) som är ett svårt problem för parametriserbara och flexibla plattformar. Avhandlingen presenterar två generationer av Tahmuras, som är baserade på villkorsprogrammering och har som mål att konstruera DSE-problemet som en komposition av tre olika delproblem: applikation, plattform, och bindning. Ett integrerat DSE-problem kan sedan automatiskt genereras genom en kombination av dessa delproblem. Olika metoder, från heuristisk till komplett sökning, kan användas inom villkorsprogrammering för att lösa DSE-problemet. För att visa Tahmuras potential har DSE-metoden validerats med hjälp av olika systemapplikationer av skilda tidsegenskaper och olika plattformar. 

Place, publisher, year, edition, pages
Stockholm: KTH Royal Institute of Technology, 2014. , xvi, 104 p.
Series
TRITA-ICT-ECS AVH, ISSN 1653-6363 ; 14:12
National Category
Embedded Systems
Identifiers
URN: urn:nbn:se:kth:diva-155939ISBN: 978-91-7595-286-4 (print)OAI: oai:DiVA.org:kth-155939DiVA: diva2:763532
Public defence
2014-12-05, Sal B, Electrum 229, KTH-ICT, Kista, 13:00 (English)
Opponent
Supervisors
Note

QC 20141117

Available from: 2014-11-17 Created: 2014-11-15 Last updated: 2014-11-17Bibliographically approved
List of papers
1. Co-simulation of embedded systems in a heterogeneous MoC-based modeling framework
Open this publication in new window or tab >>Co-simulation of embedded systems in a heterogeneous MoC-based modeling framework
2011 (English)In: 2011 6th IEEE International Symposium on Industrial Embedded Systems (SIES): Proceedings of a meeting held 15-17 June 2011, Vasteras, Sweden., IEEE Press, 2011, 238-247 p.Conference paper, Published paper (Refereed)
Abstract [en]

New design methodologies and modeling frameworks are required to provide a solution for integrating legacy code and IP models in order to be accepted in the industry. To tackle this problem, we introduce the concept of wrappers in the context of a formal heterogeneous embedded system modeling framework. The formalism is based on the language-independent concept of models of computation. Wrappers enable the framework to co-simulate/co-execute with external models which might be legacy code, an IP block, or an implementation of a partially refined system. They are defined formally in order to keep the analyzability of the original framework and also enable automations such as generation of model wrappers and co-simulation interfaces. As a proof of concept, three wrappers for models in different abstraction levels are introduced and implemented for two case studies.

Place, publisher, year, edition, pages
IEEE Press, 2011
Keyword
Adaptation models, Computational modeling, Computer architecture, embedded systems, Engines, Semantics, synchronization
National Category
Embedded Systems
Identifiers
urn:nbn:se:kth:diva-46477 (URN)10.1109/SIES.2011.5953667 (DOI)2-s2.0-80051988074 (Scopus ID)9781612848181 (ISBN)
Conference
2011 6th IEEE International Symposium on Industrial Embedded Systems (SIES)
Funder
EU, FP7, Seventh Framework Programme
Note
© 2011 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. QC 20110202Available from: 2012-02-02 Created: 2011-11-03 Last updated: 2014-11-17Bibliographically approved
2. Semi-formal refinement of heterogeneous embedded systems by foreign model integration
Open this publication in new window or tab >>Semi-formal refinement of heterogeneous embedded systems by foreign model integration
2011 (English)In: 2011 Forum on Specification and Design Languages (FDL), IEEE conference proceedings, 2011, 179-186 p.Conference paper, Published paper (Refereed)
Abstract [en]

There is a need for integration of external models in high-level system design flows. We introduce a set of partial refinement operations to implement models of heterogeneous embedded systems. The models are in form of process networks where each process belongs to a single model of computation. A semi-formal design flow has been introduced based on these operations to incrementally refine system specifications to their implementation. Wrapper processes, which allow co-simulation of a system model in the framework with external models and implementations are used to keep the intermediate system models after each refinement step verifiable. Additionally, this design flow has the advantage of integrating legacy code and IP cores. Using a simple example as the case study, we have shown how we can apply this design methodology to a simple system.

Place, publisher, year, edition, pages
IEEE conference proceedings, 2011
Keyword
Adaptation models, Computational modeling, Data models, embedded systems, foreign model integration, formal specification, formla system design, ForSyDe, Hardware, hardware description languages, Hardware design languages, HDL, heterogeneous embedded systems, high-level system design, incremental system specification refinement, IP core, legacy code, partial refinement operation, process network, semiformal design flow, software, synchronization, system model, systems analysis, wrapper process
National Category
Embedded Systems
Identifiers
urn:nbn:se:kth:diva-62149 (URN)2-s2.0-82955190416 (Scopus ID)978-2-9530504-3-1 (ISBN)
Conference
2011 Forum on Specification and Design Languages (FDL)
Projects
SYSMODEL
Funder
EU, FP7, Seventh Framework Programme
Note
© 2011 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. QC 20120201Available from: 2012-02-01 Created: 2012-01-18 Last updated: 2014-11-17Bibliographically approved
3. Formal heterogeneous system modeling with SystemC
Open this publication in new window or tab >>Formal heterogeneous system modeling with SystemC
2012 (English)In: Proceedings of Forum on Specification and Design Languages (FDL) 2012, 2012, 160-167 p.Conference paper, Published paper (Refereed)
Abstract [en]

Electronic System Level (ESL) design of embedded systems proposes raising the abstraction level of the design entry to cope with the increasing complexity of such systems. To exploit the benefits of ESL, design languages should allow specification of models which are a) heterogeneous, to describe different aspects of systems; b) formally defined, for application of analysis and synthesis methods; c) executable, to enable early detection of specification; and d) parallel, to exploit the multi- and many-core platforms for simulation and implementation. We present a modeling library on top of SystemC, targeting heterogeneous embedded system design, based on four models of computation. The library has a formal basis where all elements are well defined and lead in construction of analyzable models. The semantics of communication and computation are implemented by the library, which allows the designer to focus on specifying the pure functional aspects. A key advantage is that the formalism is used to export the structure and behavior of the models via introspection as an abstract representation for further analysis and synthesis.

Keyword
Modeling, Simulation, System-level design, Computer aided engineering, Formal specifications
National Category
Embedded Systems
Identifiers
urn:nbn:se:kth:diva-104557 (URN)2-s2.0-84871051725 (Scopus ID)978-1-4673-1240-0 (ISBN)
Conference
Forum on Specification and Design Languages (FDL) 2012
Projects
SYSMODEL
Note

QC 20130122

Available from: 2013-01-11 Created: 2012-11-05 Last updated: 2014-11-17Bibliographically approved
4. Heterogeneous system-level modeling for small and medium enterprises
Open this publication in new window or tab >>Heterogeneous system-level modeling for small and medium enterprises
Show others...
2012 (English)In: Integrated Circuits and Systems Design (SBCCI), 2012 25th Symposium on, IEEE conference proceedings, 2012, 1-6 p.Conference paper, Published paper (Refereed)
Abstract [en]

The design of today's electronic embedded systems is an increasingly complicated task. This is especially problematic for Small and Medium Enterprises (SMEs) which have limited resources. In this work, we identify a set of common design practices used in industry, with a special focus on problems faced by smaller companies, and formulate them as design scenarios. We show how SMEs can benefit from a system-level design approach by customizing a formal heterogeneous system modeling framework for each scenario. The applicability of this approach is demonstrated by two industrial use cases, an impulse-radio radar and a UART-based protocol.

Place, publisher, year, edition, pages
IEEE conference proceedings, 2012
Keyword
Design practice, Heterogeneous systems, Impulse radios, Industrial use, Small and medium enterprise, System level design, System-level modeling
National Category
Embedded Systems
Identifiers
urn:nbn:se:kth:diva-111428 (URN)10.1109/SBCCI.2012.6344450 (DOI)2-s2.0-84870840507 (Scopus ID)978-1-4673-2606-3 (ISBN)
Conference
2012 25th Symposium on Integrated Circuits and Systems Design, SBCCI 2012; Brasilia; 30 August 2012 through 2 September 2012
Note

QC 20130121

Available from: 2013-01-11 Created: 2013-01-11 Last updated: 2014-11-17Bibliographically approved
5. An Automated Parallel Simulation Flow for Heterogeneous Embedded Systems
Open this publication in new window or tab >>An Automated Parallel Simulation Flow for Heterogeneous Embedded Systems
2013 (English)In: Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013, 2013, 27-30 p.Conference paper, Published paper (Refereed)
Abstract [en]

Simulation of complex embedded and cyber-physical systems requires exploitation of the computation power ofavailable parallel architectures. Current simulation environments either do not address this parallelism or use separate models for parallel simulation and for analysis and synthesis, which might lead to model mismatches. We extend a formal modeling framework targeting heterogeneous systems with elements that enable parallel simulations. An automated flow is then proposed that starting from a serial executable specification generates an efficient MPI-based parallel simulation model by using aconstraint-based method. The proposed flow generates parallel models with acceptable speedups for a representative example.

Series
Design, Automation, and Test in Europe Conference and Exhibition. Proceedings, ISSN 1530-1591
National Category
Embedded Systems
Identifiers
urn:nbn:se:kth:diva-121772 (URN)10.7873/DATE.2013.020 (DOI)2-s2.0-84885575736 (Scopus ID)978-1-4673-5071-6 (ISBN)
Conference
Design, Automation & Test in Europe (DATE'13); Grenoble, France, 18-22 March 2013
Note

QC 20130822

Available from: 2013-05-03 Created: 2013-05-03 Last updated: 2014-11-17Bibliographically approved
6. A Framework for Characterizing Predictable Platform Templates
Open this publication in new window or tab >>A Framework for Characterizing Predictable Platform Templates
2014 (English)Report (Other academic)
Abstract [en]

The design of real-time multiprocessor systems is a very costly and time-consuming process due to the need for extensive verification efforts. Genericcorrect-by-construction system-level design flows, targeting predictable plat-forms, would help to tackle this problem. Unfortunately, because system-level design problems are formulated monolithically, existing methods areeither not powerful enough to perform efficient design space exploration,over-customized to a specific class of platforms, or do not allow to be ex-tended with new heuristics and solving methods, which makes their reusedifficult. We present a formal framework to explicitly capture and character-ize predictable platform templates that can be used to formulate a genericdesign flow for real-time streaming applications in a composable manner. Aproof-of-concept implementation of such a flow is performed and used to mapa JPEG encoder application onto an FPGA-based time-predictable platform.

Place, publisher, year, edition, pages
Stockholm, Sweden: KTH Royal Institute of Technology, 2014. 18 p.
Series
TRITA-ICT/ECS R, ISSN 1653-7238 ; 14:01
Keyword
automation, design-space exploration, predictable platforms, real-time systems
National Category
Embedded Systems
Identifiers
urn:nbn:se:kth:diva-148162 (URN)KTH/ICT/ECS/R-14-01-SE (ISRN)
Note

QC 20140819

Available from: 2014-08-01 Created: 2014-08-01 Last updated: 2014-11-17Bibliographically approved
7. Automatic Generation of Virtual Prototypes from Platform Templates
Open this publication in new window or tab >>Automatic Generation of Virtual Prototypes from Platform Templates
2015 (English)In: Languages, Design Methods, and Tools for Electronic System Design: Selected Contributions from FDL 2013 / [ed] Marie-Minerve Louërat, Torsten Maehne, Switzerland: Springer, 2015, 147-166 p.Chapter in book (Refereed)
Abstract [en]

Virtual Prototypes (VPs) provide an early development platform to embedded software designers when the hardware is not ready yet and allows them to explore the design space of a system, both from the software and architecture perspective. However, automatic generation of VPs is not straightforward because several aspects such as the validity of the generated platforms and the timing of the components needs to be considered. To address this problem, based on a framework which characterizes predictable platform templates, we propose a method for automated generation of VPs which is integrated into a combined design flow consisting of analytic and simulation based design-space exploration. Using our approach the valid TLM-2.0-based simulated VP instances with timing annotation can be generated automatically and used for further development of the system in the design flow. We have demonstrated the potential of our method by designing a JPEG encoder system.

Place, publisher, year, edition, pages
Switzerland: Springer, 2015
Series
Lecture Notes in Electrical Engineering, ISSN 1876-1100 ; 311
Keyword
Design automation, Design Space Exploration (DSE), Predictable platforms, Real-time systems, Simulation Virtual Prototype (VP), Mixed-Criticality System (MCS), Transaction-Level Modeling (TLM), Constraint programming, Analytical models, Interoperability
National Category
Embedded Systems
Identifiers
urn:nbn:se:kth:diva-155935 (URN)10.1007/978-3-319-06317-1_8 (DOI)2-s2.0-84906871426 (Scopus ID)978-3-319-06316-4 (ISBN)978-3-319-06317-1 (ISBN)
Note

QC 20141117

Available from: 2014-11-15 Created: 2014-11-15 Last updated: 2014-11-17Bibliographically approved
8. An extensible modeling methodology for embedded and CPS design
Open this publication in new window or tab >>An extensible modeling methodology for embedded and CPS design
(English)Manuscript (preprint) (Other academic)
Abstract [en]

Abstract models are important tools to manage the increasing complexity of system design. The choice of a modeling language for constructing models governs what types of systems can be modeled and which subsequent design activities can be performed. This is especially true for the area of embedded electronic and cyber-physical system design, which poses several challenging requirements on modeling and design methodologies. This article argues that the ForSyDe methodology with the necessary extensions can fulfill these requirements and thus qualifies for the design of tomorrow’s systems. Based on the theory of models of computation and the concept of process constructors, heterogeneous models are captured in ForSyDe with precise semantics. A refined layer of the formalism is introduced to make its denotational-style semantics easy to implement on top of the commonly used imperative languages and an open-source realization on top of the IEEE standard language SystemC is reported. The introspection mechanism is introduced to automatically export an intermediate representation of the constructed models for further analysis/synthesis by external tools. Flexibility and extensibility of ForSyDe is emphasized by integrating a new timed model of computation without central synchronization, and providing mechanisms for integrating foreign models, parallel and distributed simulation, modeling adaptive, data-parallel, and non-deterministic systems. A set of ForSyDe features are demonstrated in practice and compared to similar approaches using two relevant case studies. 

Keyword
Modeling methodologies, Cyber-physical systems, Electronic system-level, Embedded systems, Formal models, Heterogeneous systems, Models of computation, Simulation, SystemC
National Category
Embedded Systems
Identifiers
urn:nbn:se:kth:diva-155937 (URN)
Note

QS 2014

Available from: 2014-11-15 Created: 2014-11-15 Last updated: 2014-11-17Bibliographically approved
9. Automatic Construction of Models for Analytic Design Space Exploration Problems
Open this publication in new window or tab >>Automatic Construction of Models for Analytic Design Space Exploration Problems
(English)Manuscript (preprint) (Other academic)
Abstract [en]

Due to the variety of application semantics and also the target platforms used in embedded electronic system design, it is challenging to propose a generic and extensible analytic design-space exploration (DSE) framework. Current approaches support a restricted class of application and platform models and are difficult to extend. This paper proposes a framework to capture the system functionality, a flexible target platform, and a binding policy explicitly using coherent constraint-based representations; together with a method for automatic construction of DSE problem models from them. Heterogeneous semantics is captured using constraints on logical clocks. The applicability of this method is demonstrated by constructing DSE problem models from various combinations of application and platforms models. Time-triggered and untimed models of the system functionality and heterogeneous target platforms are used for this purpose. The constructed models can be solved using different solvers and heuristics. 

National Category
Embedded Systems
Identifiers
urn:nbn:se:kth:diva-155938 (URN)
Note

QS 2014

Available from: 2014-11-15 Created: 2014-11-15 Last updated: 2014-11-17Bibliographically approved

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Attarzadeh Niaki, Seyed Hosein

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