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Non-traditional architectures for AD- and DA-converters
KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
2005 (English)In: ASICON 2005: 2005 6th International Conference on ASIC, Proceedings, 2005, 417-418 p.Conference paper (Refereed)
Abstract [en]

Traditional AD-converters of cyclic or pipeline type normally use algorithms that create offset binary output code. The input sample is converted starting with the most significant bit (MSB) and ends with the least significant bit (LSB), giving a total of N bits. In cyclic converters this is achieved by one processing element resolving a number of bits, M, with the residue voltage is scaled by M and fed back to the input in a recursive manner in a loop. For pipeline converters this loop is rolled out, using one processing element for each set of M bits and using N/M processing stages. Current popular state-of-the-art converter architectures use M=1 and M=1.5, with error correction for the 1.5 bit case. Cyclic converters are normally used for medium speed operation and can be designed for extremely small silicon area and power consumption, while pipeline converters can be very high speed at the cost of more area and power consumption. Nonidealities in the processing elements, such as capacitor mismatch, amplifier and comparator offsets, signal dependent and independent charge injection, finite OTA gain- and bandwidth and noise will induce errors in the residue voltages that eventually affect the accuracy of the converter limiting its resolution [1],[2]. The errors can be both random and systematic. Normally these errors are addressed by circuit level improvements meant to reduce their magnitude. Alternately, some of the errors can be mitigated at the block level, especially the systematic errors. The use of Gray coding [3] achieves a lower accumulation of errors that depends on the bits generated. The net effect of Gray coding is to introduce only a gain difference, compared to an ideal converter. Two other alternatives are to slightly modify the Binary output code, by alternating the residue error sign at each cycle [4],[5], or alternate the sign for the MSB residue voltage [4]],[6]. These modifications improve the performance by several bits compared to traditional Binary coded converters. These improvements are obtained at no extra hardware cost, since only complementary binary outputs are needed, which are already available for fully differential realizations. For DA-converters the concept of cyclic and pipelined converters can easily be obtained, by reversing the operations for the ADC algorithms. The resulting DACs start with the LSB and the conversion is completed when the MSB is processed, either in a cyclic manner or pipelined. The input signal can be Binary coded, alternate Binary coded or Gray coded [7]-[9]. Substantial performance improvements are achievable also for DACs at the block level by modifying the digital input code format in a similar manner as for ADCs. Traditional high-performance DACs are normally built as two-stage converters, using one coarse and one fine stage using combinations of R2R ladders and Binary weighted current sources. The outputs are for most designs a current. In order to achieve low thermal noise the terminating resistor is small, resulting in a large power consumption. The techniques described above allow one to use voltages as outputs, giving potential advantages in power consumption. This paper gives a brief overview of the alternate architectures for ADCs and DACs using simple algorithm modifications at the block level and the possible performance improvements are motivated and verified.

Place, publisher, year, edition, pages
2005. 417-418 p.
Keyword [en]
Binary codes, Computer architecture, Digital to analog conversion, Pipeline processing systems, Signal encoding, Signal processing, Digital input codes, Gray coding, Least significant bit (LSB), Most significant bit (MSB), Analog to digital conversion
National Category
Electrical Engineering, Electronic Engineering, Information Engineering Computer and Information Science
URN: urn:nbn:se:kth:diva-156301ISI: 000235304100106ScopusID: 2-s2.0-33847393294ISBN: 0780392108ISBN: 9780780392106ISBN: 0780392108ISBN: 9780780392106OAI: diva2:766601
ASICON 2005: 2005 6th International Conference on ASIC, 24 October 2005 through 27 October 2005, Shanghai, China

QC 20141127

Available from: 2014-11-27 Created: 2014-11-26 Last updated: 2014-11-27Bibliographically approved

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