An on-chip low power clock multiplier unit in 0.25 micron technology
2005 (English)In: Canadian Conference on Electrical and Computer Engineering, 2005, 1735-1738 p.Conference paper (Refereed)
A new method to obtain a high frequency clock (1 GHz) from a low frequency reference clock (10 MHz) is presented in this paper. High frequency is achieved using two level sensitive flip-flops. Variable delay lines are used to ensure that the multiplied clock is running in correct frequency. In the newly designed multiplier, the low frequency reference clock itself at every of its falling and rising edge keeps the generated high frequency clock in phase. The clock multiplication is achieved with 82ps peak-to-peak jitter when the generated clock is 1 GHz and consuming 0.822mW power from 2.5 volt power supply. The performance of the multiplication unit is tested on PSPICE using BSIM3v3 model parameters in.25μm CMOS technology.
Place, publisher, year, edition, pages
2005. 1735-1738 p.
, Canadian Conference on Electrical and Computer Engineering, ISSN 0840-7789 ; 2005
Clock generator, Delay-controlled oscillator, Frequency multiplication, Low skew, Voltage controlled delay line, Clock generators, Voltage controlled delay lines, Electric delay lines, Jitter, Mathematical models, Natural frequencies, Oscillators (electronic), Flip flop circuits
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-156279DOI: 10.1109/CCECE.2005.1557318ScopusID: 2-s2.0-33751350292OAI: oai:DiVA.org:kth-156279DiVA: diva2:767508
Canadian Conference on Electrical and Computer Engineering 2005, 1 May 2005 through 4 May 2005, Saskatoon, SK, Canada
QC 201412012014-12-012014-11-262014-12-01Bibliographically approved