A nanocore/CMOS hybrid system-on-Package (SoP) architecture for future nanoelectronic systems
2005 (English)In: Nanotechnol. Conf. Trade Show Nanotech Techn. Proc., 2005, 157-160 p.Conference paper (Refereed)
Recent results showed that when the minimum feature size used in semi-conductor device fabrication moves to sub nanometre scale, several physical and economic limits jeopardize the device behaviour, binary logic, and the lithography techniques currently used. To surpass this "brick-wall" and continue the Moore's Law forever, novel nano-electronic devices are becoming more popular and promising. But, interconnecting nano-devices into complex electronic systems has not yet been demonstrated. In this paper, we propose a Nanocore/CMOS Hybrid System-on-Package (SoP) architecture which is suitable for any emerging nanotechnology.
Place, publisher, year, edition, pages
2005. 157-160 p.
, 2005 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2005 Technical Proceedings
AET cell, Error-tolerant, Hybrid, Nanocore, Nanoelectronic, System-on-package, Adders, Lithography, Nanotechnology, Semiconductor materials, Nanostructured materials
IdentifiersURN: urn:nbn:se:kth:diva-156489ScopusID: 2-s2.0-32044468551ISBN: 0976798522OAI: oai:DiVA.org:kth-156489DiVA: diva2:768275
2005 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2005, 8-12 May 2005, Anaheim, CA, USA
QC 201412032014-12-032014-11-282014-12-03Bibliographically approved