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RT-level test point insertion for sequential circuits
KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
2004 (English)In: Proceedings - 1st International Workshop on Testability Assessment, IWoTA 2004, 2004, 34-40 p.Conference paper (Refereed)
Abstract [en]

Current paper presents a new, coarse-grain method for test point insertion performed at the RT-level The method relies on inserting testability components to the RTL VHDL description of the design. The approach is based on non-classical, simplified concept of controllability and observability. The insertion takes place based on the list of uncontrollable and unobservable faults obtained by a sequential ATPG. Such interaction with an ATPG and resynthesis of the device after each test structure insertion would be very time-consuming. The proposed method solves its task with just three iterations. First, a testability analysis is carried out and controllability structures are inserted to the modules containing uncontrollable faults. Then, the circuit is resynthesized and the ATPG is run. Second, the observability structures are added to the modules, with remaining unobservable faults. Finally, after resynthesis and an ATPG run the overhead area is minimized by removing observability structures from blocks, where there was no increase in fault coverage. A synthesizable VHDL library of dedicated generic components for testability structures has been implemented. Experiments on six RTL benchmarks show the efficiency of the approach.

Place, publisher, year, edition, pages
2004. 34-40 p.
Keyword [en]
Data path, Logic synthesis tools, Register-transfer level, Test vectors, Computer aided design, Electric fault currents, Microprocessor chips, Sequential circuits, Vectors, VLSI circuits, Design for testability
National Category
Computer and Information Science
URN: urn:nbn:se:kth:diva-157280ScopusID: 2-s2.0-21444458751ISBN: 0780388518ISBN: 9780780388512OAI: diva2:771241
1st International Workshop on Testability Assessment, IWoTA 2004, 2 November 2004 through 2 November 2004, Rennes, France

QC 20141212

Available from: 2014-12-12 Created: 2014-12-08 Last updated: 2014-12-12Bibliographically approved

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Govind, Vineeth
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Microelectronics and Information Technology, IMIT
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