Performance and network power evaluation of tightly mixed SRAM NUCA for 3D Multi-core Network on Chips
2014 (English)In: 2014 IEEE International Symposium on Circuits and Systems (ISCAS), IEEE , 2014, 1961-1964 p.Conference paper (Refereed)
Last level cache (LLC) is crucial for the performance of chip multiprocessors (CMPs), while power is a significant design concern for 3D CMPs. In this paper, we focus on the SRAM-based Non-Uniform Cache Architecture (NUCA) for 3D Multi-core Network-on-Chip (McNoC) systems. A tightly mixed SRAM NUCA for 3D mesh NoC is presented and analyzed. We evaluate the performance and network power with benchmarks based on a full system simulation framework. Experiment results on 16-core 3D NoC systems show that the tightly mixed NUCA could provide up to 31.71% and on average 5.95% performance improvement compared to a base 3D NUCA scheme. The tightly mixed 3D NUCA NoC can reduce network power consumption in 1.07%-15.74% and 9.64% on average compared to a baseline 3D NoCs. Our analysis and experimental results provide a guideline to design efficient 3D NoCs with stacking NUCA.
Place, publisher, year, edition, pages
IEEE , 2014. 1961-1964 p.
, Proceedings - IEEE International Symposium on Circuits and Systems, ISSN 0271-4310
3D Chip, Multi-core, NoC, NUCA
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-157968DOI: 10.1109/ISCAS.2014.6865546ScopusID: 2-s2.0-84907403010ISBN: 978-147993432-4OAI: oai:DiVA.org:kth-157968DiVA: diva2:774158
2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014, 1 June 2014 through 5 June 2014, Melbourne, VIC, Australia
QC 201412222014-12-222014-12-182014-12-22Bibliographically approved