Customizable Coarse-grained Energy-efficient Reconfigurable Packet Processing Architecture
2014 (English)In: Proceedings Of The 2014 IEEE 25th International Conference on Application-specific Systems, Architectures and Processors (ASAP), IEEE , 2014, 30-35 p.Conference paper (Refereed)
In this paper, we present a highly customizable and rapidly reconfigurable multi-core packet processing architecture that provides energy and area efficiency while retaining flexibility. Presented architecture with its agile reconfigurability permits time-critical adaptability where resources can be re-clustered at run time in few cycles, hence, maintaining efficiency if requirements of the use-case change. We elaborate the flexibility and adaptability of our architecture and we report its evaluation results. For evaluation, we performed the widely-used UDP/IP and we compared our proposed architecture to low-power 32-bit general purpose processors, a custom ASIC implementation and a programmable protocol processor. Compared to GPP-based solutions, our architecture is 20-34 times more energy efficient while providing 2.4-4.1 times higher throughput. While retaining the programmability, the proposed solution achieved 78% of the energy efficiency of hardwired ASIC implementation. Compared to a programmable protocol processor, our solution has 2.6 times more throughput and requires only a third of the gate count. lastly, we quantified the worst-case time and average-case time required for time-critical adaptability when reconfiguration occurs during a real-life Voice-Over IP traffic.
Place, publisher, year, edition, pages
IEEE , 2014. 30-35 p.
, Proceedings IEEE International Conference of Application-Specific Systems Architectures and Processors, ISSN 2160-0511
Application specific integrated circuits, Architecture, Energy efficiency, Network architecture, Packet networks, Voice/data communication systems, Area efficiency, Energy efficient, General purpose processors, Packet-processing architectures, Programmability, Proposed architectures, Reconfigurability, Reconfigurable
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-158311DOI: 10.1109/ASAP.2014.6868627ISI: 000345737000005ScopusID: 2-s2.0-84906330401OAI: oai:DiVA.org:kth-158311DiVA: diva2:776173
25th IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2014, Zurich, Switzerland, 18 June 2014 through 20 June 2014
QC 201501072015-01-072015-01-072015-01-07Bibliographically approved