A Hierarchical Reconfigurable Micro-coded Multi-core Processor for IoT Applications
2014 (English)In: 2014 9TH INTERNATIONAL SYMPOSIUM ON RECONFIGURABLE AND COMMUNICATION-CENTRIC SYSTEMS-ON-CHIP (RECOSOC), 2014Conference paper (Refereed)
This paper presents a micro-coded multi-core processor featuring reconfigurability and scalability with high energy efficiency for IoT domain-specific applications. By simplifying the control logic and removing the pipelines, the gate count of one core is minimized to 14 K. Meanwhile, all the hardware units are directly controlled and can be reorganized by the long microinstructions. High utilization of the hardware is thus achieved when designing the micro programs properly. Furthermore, both the ISAs for C and Java have been implemented by the micro programs to supply the general-purpose programmability. Besides, application-specific instructions can be further developed once higher performance is demanded in specific scenarios. Depending on the performance requirement, the activity and working strategies of the cores are adjustable. Moreover, several processors can be further connected to construct a network with the integrated router for even higher performance. As a case study, the AES encryption is implemented using both C and micro programs. More than 10 times of performance improvement is achieved when using micro programs on the single core, and 20 times on two cores.
Place, publisher, year, edition, pages
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-158848DOI: 10.1109/ReCoSoC.2014.6861360ISI: 000345225900030ScopusID: 2-s2.0-84905650394ISBN: 978-1-4799-5810-8OAI: oai:DiVA.org:kth-158848DiVA: diva2:782516
9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), MAY 26-28, 2014, Montpellier, FRANCE
QC 201501212015-01-212015-01-122015-10-09Bibliographically approved