Influence of Passivation Oxide Thickness and Device Layout on the Current Gain of SiC BJTs
2015 (English)In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 36, no 1, 11-13 p.Article in journal (Refereed) Published
The effect of passivation oxide thickness and layout on the current gain of SiC bipolar junction transistors is reported. Different thicknesses of plasma enhanced chemical vapor deposited (PECVD) silicon dioxide in the range 50-150 nm were deposited prior to the same annealing process in N2O, and their effect on the transistor gain was investigated for different device layouts. For a fixed device layout, similar to 60% higher gains were observed for oxide thicknesses ranging between 100 and 150 nm with current gains of similar to 200 at room temperature and >100 at 300 degrees C. For each tested thickness of deposited oxide, device layout providing lower collector resistance achieved slightly higher gains.
Place, publisher, year, edition, pages
IEEE Press, 2015. Vol. 36, no 1, 11-13 p.
Bipolar junction transistor (BJT), silicon carbide (SiC), current gain, deposited oxide, nitridation, surface passivation
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-159356DOI: 10.1109/LED.2014.2372036ISI: 000347045200005ScopusID: 2-s2.0-84920118646OAI: oai:DiVA.org:kth-159356DiVA: diva2:784765
FunderSwedish Foundation for Strategic Research , RE10-0011
QC 201501302015-01-302015-01-292015-04-10Bibliographically approved