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Morphable Compression Architecture for Efficient Configuration in CGRAs
KTH, School of Information and Communication Technology (ICT), Electronic Systems. University of Turku, Finland.
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
KTH, School of Information and Communication Technology (ICT), Electronic Systems. University of Turku, Finland.
KTH, School of Information and Communication Technology (ICT), Electronic Systems.ORCID iD: 0000-0003-0565-9376
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2014 (English)In: 2014 17th Euromicro Conference on Digital System Design (DSD), 2014, 42-49 p.Conference paper, Published paper (Refereed)
Abstract [en]

Today, Coarse Grained Reconfigurable Architectures (CGRAs) host multiple applications. Novel CGRAs allow each application to exploit runtime parallelism and time sharing. Although these features enhance the power and silicon efficiency, they significantly increase the configuration memory overheads (up to 50% area of the overall platform). As a solution to this problem researchers have employed statistical compression, intermediate compact representation, and multicasting. Each of these techniques has different properties (i.e. compression ratio and decoding time), and is therefore best suited for a particular class of applications (and situation). However, existing research only deals with these methods separately. In this paper we propose a morphable compression architecture that interleaves these techniques in a unique platform. The proposed architecture allows each application to enjoy a separate compression/decompression hierarchy (consisting of various types and implementations of hardware/software decoders) tailored to its needs. Thereby, our solution offers minimal memory while meeting the required configuration deadlines. Simulation results, using different applications (FFT, Matrix multiplication, and WLAN), reveal that the choice of compression hierarchy has a significant impact on compression ratio (from configware replication to 52%) and configuration cycles (from 33 nsec to 1.5 secs) for the tested applications. Synthesis results reveal that introducing adaptivity incurs negligible additional overheads (1%) compared to the overall platform area.

Place, publisher, year, edition, pages
2014. 42-49 p.
Keyword [en]
Reconfigurable computing
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Computer Science
Identifiers
URN: urn:nbn:se:kth:diva-160499DOI: 10.1109/DSD.2014.36ISI: 000358409000007Scopus ID: 2-s2.0-84928796958OAI: oai:DiVA.org:kth-160499DiVA: diva2:789962
Conference
17th Euromicro Conference on Digital System Design, DSD 2014; Verona; Italy; 27 August 2014 through 29 August 2014
Note

QC 20150416

Available from: 2015-02-21 Created: 2015-02-21 Last updated: 2015-08-27Bibliographically approved

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Hemani, Ahmed

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