Change search
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf
TransPar: Transformation based dynamic Parallelism for low power CGRAs
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
Show others and affiliations
2014 (English)In: Conference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014, 2014Conference paper, Published paper (Refereed)
Abstract [en]

Coarse Grained Reconfigurable Architectures (CGRAs) are emerging as enabling platforms to meet the high performance demanded by modern applications (e.g. 4G, CDMA, etc.). Recently proposed CGRAs offer runtime parallelism to reduce energy consumption (by lowering voltage/frequency). To implement the runtime parallelism, CGRAs commonly store multiple compile-time generated implementations of an application (with different degree of parallelism) and select the optimal version at runtime. However, the compile-time binding incurs excessive configuration memory overheads and/or is unable to parallelize an application even when sufficient resources are available. As a solution to this problem, we propose Transformation based dynamic Parallelism (TransPar). TransPar stores only a single implementation and applies a series for transformations to generate the bitstream for the parallel version. In addition, it also allows to displace and/or rotate an application to parallelize in resource constrained scenarios. By storing only a single implementation, TransPar offers significant reductions in configuration memory requirements (up to 73% for the tested applications), compared to state of the art compaction techniques. Simulation and synthesis results, using real applications, reveal that the additional flexibility allows up to 33% energy reduction compared to static memory based parallelism techniques. Gate level analysis reveals that TransPar incurs negligible silicon (0.2% of the platform) and timing (6 additional cycles per application) penalty.

Place, publisher, year, edition, pages
2014.
National Category
Computer Systems
Identifiers
URN: urn:nbn:se:kth:diva-160500DOI: 10.1109/FPL.2014.6927485Scopus ID: 2-s2.0-84911164987ISBN: 9783000446450 (print)OAI: oai:DiVA.org:kth-160500DiVA: diva2:789963
Conference
24th International Conference on Field Programmable Logic and Applications, FPL 2014; Technische Universitat MunchenMunich; Germany; 1 September 2014 through 5 September 2014
Note

QC 20150417

Available from: 2015-02-21 Created: 2015-02-21 Last updated: 2015-04-17Bibliographically approved

Open Access in DiVA

No full text

Other links

Publisher's full textScopus

Authority records BETA

Hemani, Ahmed

Search in DiVA

By author/editor
Jafri, Syed Mohammad Asad HassanDaneshtalab, MasoudHemani, AhmedPlosila, JuhaTenhunen, Hannu
By organisation
Electronic Systems
Computer Systems

Search outside of DiVA

GoogleGoogle Scholar

doi
isbn
urn-nbn

Altmetric score

doi
isbn
urn-nbn
Total: 100 hits
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf