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RuRot: Run-time rotatable-expandable partitions for efficient mapping in CGRAs
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
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2014 (English)In: Proceedings - International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, SAMOS 2014, 2014, 233-241 p.Conference paper, Published paper (Refereed)
Abstract [en]

Today, Coarse Grained Reconfigurable Architectures (CGRAs) host multiple applications, with arbitrary communication and computation patterns. Compile-time mapping decisions are neither optimal nor desirable to efficiently support the diverse and unpredictable application requirements. As a solution to this problem, recently proposed architectures offer run-time remapping. The run-time remappers displace or expand (parallelize/serialize) an application to optimize different parameters (such as platform utilization). However, the existing remappers support application displacement or expansion in either horizontal or vertical direction. Moreover, most of the works only address dynamic remapping in packet-switched networks and therefore are not applicable to the CGRAs that exploit circuitswitching for low-power and high predictability. To enhance the optimality of the run-time remappers, this paper presents a design framework called Run-time Rotatable-expandable Partitions (RuRot). RuRot provides architectural support to dynamically remap or expand (i.e. parallelize) the hosted applications in CGRAs with circuit-switched interconnects. Compared to state of the art, the proposed design supports application rotation (in clockwise and anticlockwise directions) and displacement (in horizontal and vertical directions), at run-time. Simulation results using a few applications reveal that the additional flexibility enhances the device utilization, significantly (on average 50 % for the tested applications). Synthesis results confirm that the proposed remapper has negligible silicon (0.2 % of the platform) and timing (2 cycles per application) overheads.

Place, publisher, year, edition, pages
2014. 233-241 p.
National Category
Embedded Systems
Identifiers
URN: urn:nbn:se:kth:diva-160501DOI: 10.1109/SAMOS.2014.6893216ISI: 000361019300029Scopus ID: 2-s2.0-84907900197ISBN: 9781479937707 (print)OAI: oai:DiVA.org:kth-160501DiVA: diva2:789964
Conference
14th International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, SAMOS 2014; Samos; Greece; 14 July 2014 through 17 July 2014
Note

QC 20150417

Available from: 2015-02-21 Created: 2015-02-21 Last updated: 2015-10-08Bibliographically approved

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Hemani, Ahmed

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Jafri, Syed Mohammad Asad HassanDaneshtalab, MasoudHemani, AhmedPlosila, JuhaTenhunen, Hannu
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  • apa
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