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A many-core hardware acceleration platform for short read mapping problem using distributed memory interface with 3D-stacked architecture
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems.ORCID iD: 0000-0003-0565-9376
Indian Institute of Technology, Delhi, India.
2014 (English)In: 2014 International Symposium on System-on-Chip, SoC 2014, 2014, 1-8 p.Conference paper, Published paper (Refereed)
Abstract [en]

Next Generation Sequencing technologies produce huge amounts of short reads consisting randomly fragmented DNA base pair strings, while assembling poses a challenge on the mapping of short reads to a reference genome in terms of both sensitivity and execution time. In this paper, we propose a many-core hardware acceleration platform for short read mapping based on hash-index method, which benefit from a distributed memory interface with 3D-stacked architecture for local memory access. Our design provides an amazingly 45012 times speedup over software approach for single end short reads and 21102 times for paired end reads, while also beats similar single FPGA solution for 1466 times in case of single end reads.

Place, publisher, year, edition, pages
2014. 1-8 p.
Keyword [en]
DNA, bioinformatics, distributed memory systems, genomics, memory architecture, 3D-stacked architecture, distributed memory interface, hash-index method, local memory access, many-core hardware acceleration platform, next generation sequencing technology, randomly fragmented DNA base pair strings, reference genome, short read mapping problem, single FPGA solution, single end reads, software approach, Acceleration, Bandwidth, Bioinformatics, Computer architecture, Genomics, Random access memory, Three-dimensional displays, 3D integration, VLSI, bioinformatics, computational biology, genetics, short read mapping
National Category
Embedded Systems Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-160535DOI: 10.1109/ISSOC.2014.6972452Scopus ID: 2-s2.0-84919343986OAI: oai:DiVA.org:kth-160535DiVA: diva2:790100
Conference
2014 16th International Symposium on System-on-Chip, SoC 2014; Tampere HallYliopistonkatu 55Tampere; Finland; 28 October 2014 through 29 October 2014
Note

QC 20150410

Available from: 2015-02-23 Created: 2015-02-23 Last updated: 2017-06-15Bibliographically approved

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Hemani, Ahmed

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CiteExportLink to record
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Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
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Language
  • de-DE
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  • Other locale
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Output format
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