Interfacial layer engineering using thulium silicate/germanate for high-k/metal gate MOSFETs
2014 (English)In: ECS Transactions: Cancun, Mexico, October 5 – 9, 2014 2014 ECS and SMEQ Joint International Meeting, Electrochemical Society, 2014, no 6, 249-260 p.Conference paper (Refereed)
Thulium silicate (TmSiO) is considered as high-k interfacial layer in high-k/metal gate stacks, providing advantages in terms of EOT scalability and enhanced inversion layer mobility. In this work, we show that optimized annealing conditions for the TmSiO/HfO2/TiN gate stack provide competitive gate leakage current density, symmetric nFET and pFET threshold voltages, while retaining compatibility with CMOS processing and ∼20% higher electron and hole mobility than literature data on optimized SiOx/HfO2 stacks at EOT as low as 0.65 nm. We also evaluate cleaning procedures to facilitate thulium germanate formation on Ge channel materials and found that HF cleaning optimization is needed to allow thulium germanate formation while keeping surface roughness at an acceptable level.
Place, publisher, year, edition, pages
Electrochemical Society, 2014. no 6, 249-260 p.
, ECS Transactions, ISSN 1938-5862 ; 64
Field effect transistors, Germanium, Hole mobility, Leakage currents, Logic gates, Silicates, Silicon alloys, Surface roughness, Threshold voltage, Thulium, Channel materials, Cleaning procedures, CMOS processing, Gate leakage current density, High-k/metal gates, Interfacial layer, Literature data, Optimized annealing conditions
Other Materials Engineering
IdentifiersURN: urn:nbn:se:kth:diva-160674DOI: 10.1149/06406.0249ecstScopusID: 2-s2.0-84921283600OAI: oai:DiVA.org:kth-160674DiVA: diva2:790886
6th SiGe, Ge, and Related Compounds: Materials, Processing and Devices Symposium - 2014 ECS and SMEQ Joint International Meeting, Cancun, Mexico, 5 October 2014 through 9 October 2014
FunderSwedish Foundation for Strategic Research
QC 201502262015-02-262015-02-262015-02-26Bibliographically approved