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An analytical model for worst-case reorder buffer size of multi-path minimal routing NoCs
KTH, School of Information and Communication Technology (ICT), Electronic Systems.ORCID iD: 0000-0003-0061-3475
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2014 (English)In: Proceedings - 2014 8th IEEE/ACM International Symposium on Networks-on-Chip, NoCS 2014, IEEE , 2014, 49-56 p.Conference paper (Refereed)
Abstract [en]

Reorder buffers are often needed in multi-path routing networks-on-chips (NoCs) to guarantee in-order packet delivery. However, the buffer sizes are usually over-dimensioned, due to lack of worst-case analysis, leading to unnecessary larger area overhead. Based on network calculus, we propose an analysis framework for the worst-case reorder buffer size in multi-path minimal routing NoCs. Experiments with synthetic traffic and an industry case show that our method can effectively explore the traffic splitting space, as well as the mapping effects in terms of reorder buffer size with a maximum improvement of 36.50%.

Place, publisher, year, edition, pages
IEEE , 2014. 49-56 p.
Keyword [en]
Calculations, Microprocessor chips, Network-on-chip, Program compilers, Recording instruments, Analysis frameworks, Area overhead, In-order packet delivery, Multi path routing, Network calculus, Re-order buffers, Traffic splitting, Worst-case analysis
National Category
Communication Systems
URN: urn:nbn:se:kth:diva-160659DOI: 10.1109/NOCS.2014.7008761ScopusID: 2-s2.0-84922559641ISBN: 9781479953479OAI: diva2:791107
8th IEEE/ACM International Symposium on Networks-on-Chip, NoCS 2014, Ferrara, Italy, 17 September 2014 through 19 September 2014

QC 20150226

Available from: 2015-02-26 Created: 2015-02-26 Last updated: 2015-02-26Bibliographically approved

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Lu, Zhonghai
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