A Novel Congestion Control Scheme in Network-on-Chip Based on Best Effort Delay-Sum Optimization
2008 (English)In: Proceedings of the International Symposium on Parallel Architectures, Algorithms and Networks, I-SPAN, 2008, 191-196 p.Conference paper (Refereed)
With the advances of the semiconductor technology, the enormous number of transistors available on a single chip allows designers to integrate dozens of IP blocks together with large amounts of embedded memory. This has been led to the concept of network on a chip (NoC), in which different modules would be connected by a simple network of shared links and routers and is considered as a solution to replace traditional bus-based architectures to address the global communication challenges in nanoscale technologies. In NoC architectures, controlling congestion of the best effort traffic will continue to be an important design goal. Towards this, employing end-to-end congestion control is becoming more imminent in the design process of NoCs. In this paper, we introduce a centralized algorithm based on the delay minimization of best effort sources. The proposed algorithm can be used as a mechanism to control the flow of best effort source rates by which the sum of propagation delays of network is to be minimized.
Place, publisher, year, edition, pages
2008. 191-196 p.
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-161079DOI: 10.1109/I-SPAN.2008.45ScopusID: 2-s2.0-49149097088ISBN: 978-0-7695-3125-0OAI: oai:DiVA.org:kth-161079DiVA: diva2:793758
International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN)
QC 201503102015-03-092015-03-092015-03-10Bibliographically approved