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Max-Min-Fair Best Effort Flow Control in Network-on-Chip Architectures
Ferdowsi University of Mashhad, Mashhad, Iran .
2008 (English)In: Computational Science – ICCS 2008, 2008, 436-445 p.Conference paper, Published paper (Refereed)
Abstract [en]

Network-on-Chip (NoC) has been proposed as an attractive alternative to traditional dedicated busses in order to achieve modularity and high performance in the future System-on-Chip (SoC) designs. Recently, end to end flow control has gained popularity in the design process of network-on-chip based SoCs. Where flow control is employed, fairness issues need to be considered as well. In fact, one of most difficult aspects of flow control is that of treating all sources fairly when it is necessary to turn traffic away from the network. In this paper, we proposed a flow control scheme which admits Max-Min fairness criterion for all sources. In fact, we formulated Max-Min fairness criterion for the NoC architecture and presented implementation to be used as flow control mechanism.

Place, publisher, year, edition, pages
2008. 436-445 p.
Series
Lecture notes in computer science, ISSN 0302-9743 ; 5010
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-161080DOI: 10.1007/978-3-540-69384-0_49Scopus ID: 2-s2.0-47749155242ISBN: 978-354069383-3 (print)OAI: oai:DiVA.org:kth-161080DiVA: diva2:793764
Conference
8th International Conference on Computational Science, ICCS 2008; Krakow; Poland
Note

QC 20150310

Available from: 2015-03-09 Created: 2015-03-09 Last updated: 2015-03-10Bibliographically approved
In thesis
1. Analysis and Management of Communication in On-Chip Networks
Open this publication in new window or tab >>Analysis and Management of Communication in On-Chip Networks
2015 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

Regarding the needs of low-power, high-performance embedded systems and the growing computation-intensive applications, the number of computing resources in a single chip has enormously increased. The current VLSI technology is able to support such an integration of transistors and add many computing resources such as CPU, DSP, specific IPs, etc to build a Systemon- Chip (SoC). However, interconnection between resources becomes another challenging issue which can be raised by using an on-chip interconnection network or Network-on-Chip (NoC). NoC-based communication which allows pipelined concurrent transmissions of transactions is becoming a dominate infrastructure for many core computing platforms.

This thesis analyzes and manages both Best Effort (BE) and Guaranteed Service (GS) communications using analytical performance approaches. As the first step, the present thesis focuses on the flow control for BE traffic in NoC. It models BE source rates as the solution to a utility-based optimization problem which is constrained with link capacities while preserving GS traffic requirements at the desired level. Towards this, several utility functions including proportionally-fair, rate-sum, and max-min fair scenarios are investigated. Moreover, it is worth looking into a scenario in which BE source rates are determined in favor of minimizing the delay of such traffics. The presented flow control algorithms solve the proposed optimization problems determining injection rate in each BE source node.

In the next step, real-time systems with guaranteed service are considered. Real-time applications require performance guarantees even under worst-case conditions, i.e. Quality of Service (QoS). Using network calculus, we present and prove the required theorems for deriving performance metrics and then apply them to propose formal approaches for the worst-case performance analysis. The proposed analytical model is used to minimize total cost in the networks in terms of buffer and delay. To this end, we address several optimization problems and solve them to consider the impact of various objective functions. We also develop a tool which derives performance metrics for a given NoC, formulates and solves the considerable optimization problems to provide an invaluable insight for NoC designers.

Place, publisher, year, edition, pages
Stockholm: KTH Royal Institute of Technology, 2015. xxi, 59 p.
Series
TRITA-ICT-ECS AVH, ISSN 1653-6363 ; 15:01
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-161178 (URN)978-91-7595-458-5 (ISBN)
Public defence
2015-03-30, Sal/hall C, Elektrum , KTH-ICT, Isafjordsgatan, Kista, 13:00 (English)
Opponent
Supervisors
Note

QC 20150310

Available from: 2015-03-10 Created: 2015-03-09 Last updated: 2015-03-10Bibliographically approved

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Citation style
  • apa
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