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Proportionally fair flow control mechanism for best effort traffic in network-on-chip architectures
School of Computer Science, IPM, Tehran, Iran .
2010 (English)In: International Journal of Parallel, Emergent and Distributed Systems, ISSN 1744-5760, E-ISSN 1744-5779, Vol. 25, no 4, 345-362 p.Article in journal (Refereed) Published
Abstract [en]

The research community has recently witnessed the emergence of multi-processor system on chip (MPSoC) platforms consisting of a large set of embedded processors. Particularly, Interconnect networks methodology based on network-on-chip (NoC) in MPSoC design is imminent to achieve high performance potential. More importantly, many well established schemes of networking and distributed systems inspire NoC design methodologies. Employing end-to-end congestion control is becoming more imminent in the design process of NoCs. This paper presents a centralised congestion control scheme in the presence of both elastic and streaming flow traffic mixture. We model the desired best effort source rates as the solution to an optimisation problem with weighted logarithmic objective which is known to admit proportional fairness criterion. The problem is constrained with link capacities while preserving guaranteed service traffics services requirements at the desired level. We propose an iterative algorithm as the solution to the optimisation problem which has the benefit of low complexity and fast convergence, and can be implemented by a controller unit with low computation and communication overhead.

Place, publisher, year, edition, pages
2010. Vol. 25, no 4, 345-362 p.
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-161083DOI: 10.1080/17445760902894647Scopus ID: 2-s2.0-77954610437OAI: oai:DiVA.org:kth-161083DiVA: diva2:793777
Note

QC 20150310

Available from: 2015-03-09 Created: 2015-03-09 Last updated: 2017-12-04Bibliographically approved
In thesis
1. Analysis and Management of Communication in On-Chip Networks
Open this publication in new window or tab >>Analysis and Management of Communication in On-Chip Networks
2015 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

Regarding the needs of low-power, high-performance embedded systems and the growing computation-intensive applications, the number of computing resources in a single chip has enormously increased. The current VLSI technology is able to support such an integration of transistors and add many computing resources such as CPU, DSP, specific IPs, etc to build a Systemon- Chip (SoC). However, interconnection between resources becomes another challenging issue which can be raised by using an on-chip interconnection network or Network-on-Chip (NoC). NoC-based communication which allows pipelined concurrent transmissions of transactions is becoming a dominate infrastructure for many core computing platforms.

This thesis analyzes and manages both Best Effort (BE) and Guaranteed Service (GS) communications using analytical performance approaches. As the first step, the present thesis focuses on the flow control for BE traffic in NoC. It models BE source rates as the solution to a utility-based optimization problem which is constrained with link capacities while preserving GS traffic requirements at the desired level. Towards this, several utility functions including proportionally-fair, rate-sum, and max-min fair scenarios are investigated. Moreover, it is worth looking into a scenario in which BE source rates are determined in favor of minimizing the delay of such traffics. The presented flow control algorithms solve the proposed optimization problems determining injection rate in each BE source node.

In the next step, real-time systems with guaranteed service are considered. Real-time applications require performance guarantees even under worst-case conditions, i.e. Quality of Service (QoS). Using network calculus, we present and prove the required theorems for deriving performance metrics and then apply them to propose formal approaches for the worst-case performance analysis. The proposed analytical model is used to minimize total cost in the networks in terms of buffer and delay. To this end, we address several optimization problems and solve them to consider the impact of various objective functions. We also develop a tool which derives performance metrics for a given NoC, formulates and solves the considerable optimization problems to provide an invaluable insight for NoC designers.

Place, publisher, year, edition, pages
Stockholm: KTH Royal Institute of Technology, 2015. xxi, 59 p.
Series
TRITA-ICT-ECS AVH, ISSN 1653-6363 ; 15:01
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-161178 (URN)978-91-7595-458-5 (ISBN)
Public defence
2015-03-30, Sal/hall C, Elektrum , KTH-ICT, Isafjordsgatan, Kista, 13:00 (English)
Opponent
Supervisors
Note

QC 20150310

Available from: 2015-03-10 Created: 2015-03-09 Last updated: 2015-03-10Bibliographically approved

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