Accelerating Parallel Computations with OpenMP-Driven System-on-Chip Generation for FPGAs
2014 (English)In: Embedded Multicore/Manycore SoCs (MCSoc), 2014 IEEE 8th International Symposium on, IEEE conference proceedings, 2014, 149-156 p.Conference paper (Refereed)
The task-based programming paradigm offers a portable way of writing parallel applications. However, it requires tedious tuning of the application for performance. We present a novel design flow where programmers can use application knowledge to easily generate a System-on-Chip (SoC) specialized in executing the application. Our design flow uses a compiler that automatically generates task-specific cores and packs them into a custom SoC. A SoC-specific runtime systems schedules tasks on cores to accelerate application execution. The generated SoC shows up to 6000 times performance improvement in comparison to the Altera NiosII/s processor and up to 7 times compared to an AMD Opteron 6172 core. Our design flow helps programmers generate high-performance systems without requiring tuning and prior hardware design knowledge.
Place, publisher, year, edition, pages
IEEE conference proceedings, 2014. 149-156 p.
OpenMP HLS, Task-based, Hardware Generation
Research subject Computer Science
IdentifiersURN: urn:nbn:se:kth:diva-161262DOI: 10.1109/MCSoC.2014.30ISI: 000357812800021ScopusID: 2-s2.0-84917706752OAI: oai:DiVA.org:kth-161262DiVA: diva2:794345
IEEE 8th International Symposium on Embedded Multicore/Manycore SoCs (MCSoc), 23-25 Sept. 2014, Aizu-Wakamatsu
QC 201503192015-03-112015-03-112015-10-16Bibliographically approved