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Fault-tolerant routing algorithm for 3D NoC using hamiltonian path strategy
KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems. Department of Information Technology, University of Turku, Finland .
2013 (English)In: Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013, 2013, 1601-1604 p.Conference paper, Published paper (Refereed)
Abstract [en]

While Networks-on-Chip (NoC) have been increasing in popularity with industry and academia, it is threatened by the decreasing reliability of aggressively scaled transistors. In this paper, we address the problem of faulty elements by the means of routing algorithms. Commonly, fault-tolerant algorithms are complex due to supporting different fault models while preventing deadlock. When moving from 2D to 3D network, the complexity increases significantly due to the possibility of creating cycles within and between layers. In this paper, we take advantages of the Hamiltonian path to tolerate faults in the network. The presented approach is not only very simple but also able to support almost all one-faulty unidirectional links in 2D and 3D NoCs.

Place, publisher, year, edition, pages
2013. 1601-1604 p.
Keyword [en]
Fault tolerance, Fault tolerant systems, Mesh networks, Ports (Computers), Routing, Three-dimensional displays
National Category
Embedded Systems
Research subject
Electrical Engineering
Identifiers
URN: urn:nbn:se:kth:diva-162466DOI: 10.7873/DATE.2013.325OAI: oai:DiVA.org:kth-162466DiVA: diva2:797729
Conference
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013
Note

QC 20150413

Available from: 2015-03-25 Created: 2015-03-25 Last updated: 2015-04-13Bibliographically approved

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CiteExportLink to record
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Citation style
  • apa
  • harvard1
  • ieee
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  • vancouver
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More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf