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PDMS-supported Graphene Transfer Using Intermediary Polymer Layers
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.ORCID iD: 0000-0003-1234-6060
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
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2014 (English)In: PROCEEDINGS OF THE 2014 44TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE (ESSDERC 2014), 309-312 p.Article in journal (Refereed) Published
Abstract [en]

We propose a graphene transfer method based on chemical vapor deposited (CVD) graphene grown on copper foils. This transfer method utilizes a combination of a silicone elastomer (PDMS) and different intermediate polymer layers depending on the process requirements. We use polystyrene and polystyrene/photoresist intermediary layers for dry and wet graphene release. PMMA intermediary layer is applied for bubbling-assisted graphene transfer. The elastomer layer serves as an excellent solid support for electrochemical graphene delamination. Graphene-based field effect transistors (GFETs) were fabricated and characterized using this process. Raman spectroscopy was used in order to verify a successful

Place, publisher, year, edition, pages
2014. 309-312 p.
Keyword [en]
dry transfer, electrochemical, electrolysis, GFET, graphene, transfer, transistor
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
URN: urn:nbn:se:kth:diva-162024DOI: 10.1109/ESSDERC.2014.6948822ISI: 000348858100074ScopusID: 2-s2.0-84911972301ISBN: 978-1-4799-4376-0OAI: diva2:798411
44th European Solid-State Device Research Conference (ESSDERC), SEP 22-26, 2014, ITALY

QC 20150326

Available from: 2015-03-26 Created: 2015-03-20 Last updated: 2016-05-03Bibliographically approved
In thesis
1. Graphene Hot-electron Transistors
Open this publication in new window or tab >>Graphene Hot-electron Transistors
2016 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

Graphene base transistors (GBTs) have been, recently, proposed to overcome the intrinsic limitations of the graphene field effect transistors (GFETs) and exploit the graphene unique properties in high frequency (HF) applications. These devices utilize single layer graphene as the base material in the vertical hot-electron transistors. In an optimized GBT, the ultimate thinness of the graphene-base and its high conductivity, potentially, enable HF performance up to the THz region.  This thesis presents an experimental investigation on the GBTs as well as integration process developments for the fabrication of graphene-based devices.

In this work, a full device fabrication and graphene integration process were designed with high CMOS compatibility considerations. To this aim, basic process modules, such as graphene transfer, deposition of materials on graphene, and formation of tunnel barriers, were developed and optimized. A PDMS-supporting graphene transfer process were introduced to facilitate the wet/dry wafer-scale transfer from metal substrate onto an arbitrarily substrate. In addition, dielectric deposition on graphene using atomic layer deposition (ALD) was investigated. These dielectric layers, mainly, served as the base-collector insulators in the fabricated GBTs. Moreover, the integration of silicon (Si) on the graphene surface was studied.

Using the developed fabrication process, the first proof of concept devices were demonstrated. These devices utilized 5 nm-thick silicon oxide (SiO2) and about 20 nm-thick aluminum oxide (Al2O3) as the emitter-base insulator (EBI) and base-collector insulator (BCI). The direct current (DC) functionality of these devices exhibited >104 on/off current ratios and a current transfer ratio of about 6%. The performance of these devices was limited by the non-optimized barrier parameters and device manufacturing technology.

The possibility to improve and optimize the GBT performance was demonstrated by applying different barrier optimization approaches. Comparing to the proof of concept devices, several orders of magnitude higher injection current density was achieved using a bilayer dielectric tunnel barrier. Utilizing the novel TmSiO/TiO2 (1 nm/6 nm) dielectric stack, this tunnel barrier prevents defect mediated tunneling and, simultaneously, promotes the Fowler-Nordheim tunneling (FNT) and step tunneling (ST). Furthermore, it was shown that Si/graphene Schottky junction can significantly improve the current gain by reducing the electron backscattering at the base-collector barrier. In this thesis, a maximum current transfer ratio of about 35% has been achieved.

Place, publisher, year, edition, pages
Stockholm: KTH Royal Institute of Technology, 2016. xviii, 81 p.
TRITA-ICT, 2016:08
Graphene, hot-electron transistors, graphene base transistors, GBT, cross-plane carrier transport, tunneling, ballistic transport, heterojunction transistors, graphene integration, graphene transfer
National Category
Engineering and Technology
Research subject
Information and Communication Technology
urn:nbn:se:kth:diva-186044 (URN)ISBN 978-91-7595-932-0 (ISBN)
Public defence
2016-05-26, SAL C, Electrum 229, Kista, 10:00 (English)
EU, FP7, Seventh Framework Programme, 317839EU, European Research Council, 228229

QC 20160503

Available from: 2016-05-03 Created: 2016-04-29 Last updated: 2016-05-05Bibliographically approved

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