Change search
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf
Integration of TmSiO/HfO2 Dielectric Stack in Sub-nm EOT High-k/Metal Gate CMOS Technology
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.ORCID iD: 0000-0003-0333-376X
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.ORCID iD: 0000-0001-6705-1660
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.ORCID iD: 0000-0002-5845-3032
2015 (English)In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 62, no 3, 934-939 p.Article in journal (Refereed) Published
Abstract [en]

Integration of a high-k interfacial layer (IL) is a promising technological solution to improve the scalability of high-k/metal gate CMOS technology. We have previously demonstrated a CMOS-compatible integration scheme for thulium silicate (TmSiO) IL and shown excellent characteristics in terms of equivalent oxide thickness (EOT), interface state density, channel mobility, and threshold voltage control. Here, we report on optimized annealing conditions leading to gate leakage current density comparable with state-of-the-art SiOx/HfO2 nFETs (0.7 A/cm(2) at 1 V gate bias) at sub-nm EOT (as low as 0.6 nm), with near-symmetric threshold voltages (0.5 V for nFETs and -0.4 V for pFETs). We demonstrate an excellent performance benefit of the TmSiO/HfO2 stack, i.e., improved channel mobility over SiOx/HfO2 dielectric stacks, demonstrating high-field electron and hole mobility of 230 and 70 cm(2)/Vs, respectively, after forming gas anneal at EOT = 0.8 nm. Finally, the reliability of the TmSiO/HfO2/TiN gate stack is investigated, demonstrating 10-year expected life-times for both oxide integrity and threshold voltage stability at an operating voltage of 0.9 V.

Place, publisher, year, edition, pages
2015. Vol. 62, no 3, 934-939 p.
Keyword [en]
Bias temperature instability (BTI), CMOS, equivalent oxide thickness (EOT), HfO2, high-k, mobility, reliability, silicate, thulium, thulium silicate (TmSiO), time-dependent dielectric breakdown (TDDB)
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-163458DOI: 10.1109/TED.2015.2391179ISI: 000350332000037Scopus ID: 2-s2.0-84923644871OAI: oai:DiVA.org:kth-163458DiVA: diva2:800953
Funder
EU, European Research Council, OSIRIS 228229Swedish Foundation for Strategic Research
Note

QC 20150408

Available from: 2015-04-08 Created: 2015-04-07 Last updated: 2017-12-04Bibliographically approved

Open Access in DiVA

No full text

Other links

Publisher's full textScopus

Authority records BETA

Litta, Eugenio DentoniHellström, Per-Erik

Search in DiVA

By author/editor
Litta, Eugenio DentoniHellström, Per-ErikÖstling, Mikael
By organisation
Integrated Devices and Circuits
In the same journal
IEEE Transactions on Electron Devices
Other Electrical Engineering, Electronic Engineering, Information Engineering

Search outside of DiVA

GoogleGoogle Scholar

doi
urn-nbn

Altmetric score

doi
urn-nbn
Total: 99 hits
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf