Exploiting DMA for Performance and Energy Optimized STREAM on a DSP
2014 (English)In: IPDPSW ’14: Proceedings of the 2014 IEEE International Parallel & Distributed Processing Symposium Workshops, 2014, 805-814 p.Conference paper (Refereed)
Energy efficiency is of major concern in HPC.DSP architectures have the potential to offer highly competitiveenergy efficiency for applications requiring 64-bit floatingpointprecision. For STREAM, we achieved 1.47GB/J energy efficiency and 96% DDR3 memory bandwidth utilization on the Texas Instruments TMS320C6678 DSP by using its DMAengines for prefetching to avoid cache misses, which cause pipeline stalls in the DSP’s cores, and to prevent write-allocate loads, which would significantly reduce performance. The DMA engines were also used to coordinate the DSPs cores and schedule main memory accesses to improve DDR3 bandwidth utilization. We briefly describe the instrumentation that we designed and implemented for accurate measurement of the core-related, on-chip memory, and DDR3 power consumption and the effectiveness of the DSP’s power saving mechanisms to trade-off performance and energy efficiency.
Place, publisher, year, edition, pages
2014. 805-814 p.
IdentifiersURN: urn:nbn:se:kth:diva-163685DOI: 10.1109/IPDPSW.2014.92ScopusID: 2-s2.0-84918791502ISBN: 978-1-4799-4116-2OAI: oai:DiVA.org:kth-163685DiVA: diva2:801801
2014 IEEE International Parallel Distributed Processing Symposium Workshops
FunderEU, FP7, Seventh Framework Programme, RI-261557EU, FP7, Seventh Framework Programme, RI-283493Swedish National Infrastructure for Computing (SNIC)
QC 201504132015-04-102015-04-102015-04-13Bibliographically approved