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A PRET microarchitecture implementation with repeatable timing and competitive performance
University of California, Berkeley, USA.
Saarland University, Saarbrücken, Germany.
Linköpings universitet, PELAB - Laboratoriet för programmeringsomgivningar.ORCID iD: 0000-0001-8457-4105
University of California, Berkeley, USA.
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2012 (English)In: Proceedings of the 30th IEEE International Conference on Computer Design (ICCD 2012), IEEE conference proceedings, 2012, 87-93 p.Conference paper, Published paper (Refereed)
Abstract [en]

We contend that repeatability of execution times is crucial to the validity of testing of real-time systems. However, computer architecture designs fail to deliver repeatable timing, a consequence of aggressive techniques that improve average-case performance. This paper introduces the Precision-Timed ARM (PTARM), a precision-timed (PRET) microarchitecture implementation that exhibits repeatable execution times without sacrificing performance. The PTARM employs a repeatable thread-interleaved pipeline with an exposed memory hierarchy, including a repeatable DRAM controller. Our benchmarks show an improved throughput compared to a single-threaded in-order five-stage pipeline, given sufficient parallelism in the software.

Place, publisher, year, edition, pages
IEEE conference proceedings, 2012. 87-93 p.
National Category
Computer Science
Identifiers
URN: urn:nbn:se:kth:diva-163783DOI: 10.1109/ICCD.2012.6378622ISBN: 978-1-4673-3051-0 (print)OAI: oai:DiVA.org:kth-163783DiVA: diva2:803868
Conference
IEEE 30th International Conference on Computer Design(ICCD 2012), 30 september - 3 October 2012, Montreal, QC, Canada
Note

QC 20150521

Available from: 2015-04-14 Created: 2015-04-12 Last updated: 2015-05-21Bibliographically approved

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fulltext(267 kB)90 downloads
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Broman, David

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CiteExportLink to record
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Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
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More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
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  • Other locale
More languages
Output format
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