Precision Timed Infrastructure: Design Challenges
2013 (English)In: Proceedings of the Electronic System Level Synthesis Conference (ESLsyn), IEEE conference proceedings, 2013Conference paper (Refereed)
In general-purpose software applications, computation time is just a quality factor: faster is better. In cyber-physical systems (CPS), however, computation time is a correctness factor: missed deadlines for hard real-time applications, such as avionics and automobiles, can result in devastating, life-threatening consequences. Although many modern modeling languages for CPS include the notion of time, implementation languages such as C lack any temporal semantics. Consequently, models and programs for CPS are neither portable nor guaranteed to execute correctly on the real system; timing is merely a side effect of the realization of a software system on a specific hardware platform. In this position paper, we present the research initiative for a precision timed (PRET) infrastructure, consisting of languages, compilers, and microarchitectures, where timing is a correctness factor. In particular, the timing semantics in models and programs must be preserved during compilation to ensure that the behavior of real systems complies with models. We also outline new research and design challenges present in such an infrastructure.
Place, publisher, year, edition, pages
IEEE conference proceedings, 2013.
IdentifiersURN: urn:nbn:se:kth:diva-164161ISBN: 978-1-4673-6414-0OAI: oai:DiVA.org:kth-164161DiVA: diva2:803898
Electronic System Level Synthesis Conference (ESLsyn), Austin, Texas, USA, May 31-June 1, 2013
QC 201505192015-04-142015-04-142015-05-19Bibliographically approved