Change search
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf
WCET-Aware Dynamic Code Management on Scratchpads for Software-Managed Multicores
University of California, Berkeley and Arizona State University.
University of California, Berkeley and Linkoping University.ORCID iD: 0000-0001-8457-4105
Arizona State University.
University of California, Berkeley and Arizona State University.
2014 (English)In: Proceedings of the 20th IEEE Real-Time and Embedded Technology and Application Symposium (RTAS 2014), IEEE conference proceedings, 2014, p. 179-188Conference paper, Published paper (Refereed)
Abstract [en]

Software Managed Multicore (SMM) architectures have advantageous scalability, power efficiency, and predictability characteristics, making SMM particularly promising for real-time systems. In SMM architectures, each core can only access its scratchpad memory (SPM); any access to main memory is done explicitly by DMA instructions. As a consequence, dynamic code management techniques are essential for loading program code from the main memory to SPM. Current state-of-the-art dynamic code management techniques for SMM architectures are, however, optimized for average-case execution time, not worst-case execution time (WCET), which is vital for hard real-time systems. In this paper, we present two novel WCET-aware dynamic SPM code management techniques for SMM architectures. The first technique is optimal and based on integer linear programming (ILP), whereas the second technique is a heuristic that is suboptimal, but scalable. Experimental results with benchmarks from Màˆlardalen WCET suite and MiBench suite show that our ILP solution can reduce the WCET estimates up to 80% compared to previous techniques. Furthermore, our heuristic can, for most benchmarks, find the same optimal mappings within one second on a 2GHz dual core machine.

Place, publisher, year, edition, pages
IEEE conference proceedings, 2014. p. 179-188
National Category
Computer Sciences
Identifiers
URN: urn:nbn:se:kth:diva-164163DOI: 10.1109/RTAS.2014.6926001ISBN: 978-1-4799-4691-4 (print)OAI: oai:DiVA.org:kth-164163DiVA, id: diva2:803900
Conference
20th IEEE Real-Time and Embedded Technology and Application Symposium (RTAS), Berlin, Germany, 2014
Note

QC 20150512

Available from: 2015-04-14 Created: 2015-04-14 Last updated: 2018-01-11Bibliographically approved

Open Access in DiVA

fulltext(711 kB)64 downloads
File information
File name FULLTEXT01.pdfFile size 711 kBChecksum SHA-512
5f8466db8093000e3570833b45c91ccd93f741711f9032862273157744a8e8f3e5dae5b3bde1f2661f28fe4a3dbc1e600923ba94dcd11ec5dfbe882fcec1237b
Type fulltextMimetype application/pdf

Other links

Publisher's full textIEEEXplore

Authority records BETA

Broman, David

Search in DiVA

By author/editor
Broman, David
Computer Sciences

Search outside of DiVA

GoogleGoogle Scholar
Total: 64 downloads
The number of downloads is the sum of all downloads of full texts. It may include eg previous versions that are now no longer available

doi
isbn
urn-nbn

Altmetric score

doi
isbn
urn-nbn
Total: 57 hits
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf