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A Scan Partitioning Algorithm for Reducing Capture Power of Delay-Fault LBIST
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
KTH, School of Information and Communication Technology (ICT), Electronic Systems.ORCID iD: 0000-0001-7382-9408
Development Unit Radio, Ericsson AB, Sweden.
2015 (English)In: Proceedings of Design, Automation and Test in Europe Conference and Exhibition (DATE), 2015, 2015, 842-847 p.Conference paper, Published paper (Refereed)
Place, publisher, year, edition, pages
2015. 842-847 p.
Keyword [en]
BIST, delay-fault, Capture Power, scan partitioning
National Category
Computer Science
Identifiers
URN: urn:nbn:se:kth:diva-165462Scopus ID: 2-s2.0-84945946794OAI: oai:DiVA.org:kth-165462DiVA: diva2:808487
Conference
Design, Automation and Test in Europe Conference and Exhibition (DATE'2015)
Note

QC 20150508

Available from: 2015-04-28 Created: 2015-04-28 Last updated: 2015-05-08Bibliographically approved
In thesis
1. Improvements in High-Coverage and Low-Power LBIST
Open this publication in new window or tab >>Improvements in High-Coverage and Low-Power LBIST
2015 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

Testing cost is one of the major contributors to the manufacturing cost of integrated circuits. Logic Built-In Self Test (LBIST) offers test cost reduction in terms of using smaller and cheaper ATE, test data volume reduction due to on-chip test pattern generation, test time reduction due to at-speed test pattern application. However, it is difficult to reach a sufficient test coverage with affordable area overhead using LBIST. Also, excessive power dissipation during test due to the random nature of LBIST patterns causes yield-decreasing problems such as IR-drop and overheating.

In this dissertation, we present techniques and algorithms addressing these problems.

In order to increase test coverage of LBIST, we propose to use on-chip circuitry to store and generate the "top-off" deterministic test patterns. First, we study the synthesis of Registers with Non-Linear Update (RNLUs) as on-chip sequence generators. We present algorithms constructing RNLUs which generate completely and incompletely specified sequences. Then, we evaluate the effectiveness of RNLUs generating deterministic test patterns on-chip. Our experimental results show that we are able to achieve higher test coverage with less area overhead compared to test point insertion. Finally, we investigate the possibilities of integrating the presented on-chip deterministic test pattern generator with existing Design-For-Testability (DFT) techniques with a case study.

The problem of excessive test power dissipation is addressed with a scan partitioning algorithm which reduces capture power for delay-fault LBIST. The traditional S-graph model for scan partitioning does not quantify the dependency between scan cells. We present an algorithm using a novel weighted S-graph model in which the weights are scan cell dependencies determined by signal probability analysis. Our experimental results show that, on average, the presented method reduces average capture power by 50% and peak capture power by 39% with less than 2% drop in the transition fault coverage. By comparing the proposed algorithm to the original scan partitioning, we show that the proposed method is able to achieve higher capture power reduction with less fault coverage drop.

Place, publisher, year, edition, pages
Stockholm: KTH Royal Institute of Technology, 2015. xi, 84 p.
Series
TRITA-ICT-ECS AVH, ISSN 1653-6363 ; 15:05
National Category
Computer Science
Identifiers
urn:nbn:se:kth:diva-165463 (URN)978-91-7595-538-4 (ISBN)
Public defence
2015-06-01, Sal A, Isafjordsgatan 26, Kista, 13:00 (English)
Opponent
Supervisors
Note

QC 20150508

Available from: 2015-05-08 Created: 2015-04-28 Last updated: 2015-05-08Bibliographically approved

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Dubrova, Elena

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Citation style
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Output format
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